If AI capital start to be flat from 2028, then the foundry with most capacity and PPA lead (and more importantly, PPACs lead) will win. Those customer who decide to pick up 2nd wafer source will flow back XD So let’s pray for another big engine for AI capital growth to appear, like edge AI and robot. 😆

Samsung has reportedly secured orders for the entire planned output of its second chip plant in Taylor, Texas, with most capacity going to AMD. - AMD HBM base dies to be built on Samsung's 2nm process - Plant covers around 2.7 million square feet, roughly 1.5x the first Taylor fab - Construction formally begins this month - Equipment installation planned for February 2029, mass production in 2030 - Nvidia could also be served by the facility; Samsung's first Taylor plant already has a Tesla contract What this means for Samsung Foundry's fight with TSMC, on our site.

Because the video is formally rls so we can use the picture 1 XD And the decap team told me their A20 Pro decap results may have some magnitude error on the FIB/SEM image. And this time, they change the FIB lab for D9600/ 8EE6 decap, and actually they are the most closest one to the real dimension so far. Below we list the N2 dimension number from different sources: HD cell G48H130, 236.17mtr (SNPS, N2P) G47H125, 250.84mtr (TI, A20 Pro, N2) G47H127, 246.89mtr (D9600&8EE6, N2P) HP cell G48H156, 196.81mtr (SNPS, N2P) G47H150, 209.03mtr (TI, A20 Pro, N2) G47H152.5, 205.61mtr (D9600/8EE6, N2P) ———————- You may be confused for above dimension results, but remember the dimension obtained from decaping may have some image error. And previously, I have said 18A density (cell level) is 33-34% inferior to N2, and you can not obtained this value from SNPS’s data (G50H160 vs G48H130). This is because SNPS sometimes will not update the optical shrink, like N4 still be labeled as G51H210, the same as N5, but we know it has 2% optical shrink and yield in 4% density gain. Remembered, TSMC has stated that N2 and N2P have no density difference, so you should know what happen and how to interpret the above decaping dimension XD And finally, I use the precise dimension to plot the cell level density chart for different node (calculated from real dimension, not from decap results). PS1. We use cell level density, not block level density to simplify the comparison: PS2. 14A2 is bring by Wei Jan so you could see there has an optical shrink on 2031 XD 14A truely reduce the density gap from 18A >30% to 20-30% level. But that is logic. If we also consider the SRAM bitcell area gap, then the total gap will not reduce from N2 vs 18A XD (remember 18A SRAM bitcell area is tha same as N2).

Samsung is already talking to multiple customers about its most advanced foundry process. Some have confirmed chip development. The company said discussions are underway with many customers on its leading-edge 1.4-nanometer foundry process. With some of them, chip development has already been confirmed. The comments come as Samsung works to build out the 1.4-nanometer node after its 2-nanometer process.

Samsung’s earnings next year are going to be phenomenal... Take a look at this comment from Samsung’s earnings call today. Jaejune Kim, Executive Vice President of the Memory Business in Samsung Electronics’ Device Solutions (DS) division, said on the conference call following the company’s third-quarter earnings release on the 29th: “Next year’s HBM supply is already sold out, with pricing negotiations concluded at our target levels,” adding that “requests for additional volume continue to come in.” “At our target levels”... Do you realize what that means? Korean media previously reported that Samsung had quoted HBM4 prices in the mid-to-high $4 range per gigabit (Gb). (Reference: There were also rumors that NVIDIA was pushing back because it did not want to pay those prices. But judging by Samsung’s comments today, it looks like NVIDIA has ultimately accepted Samsung’s asking price. It now appears confirmed that Samsung will be selling HBM4 at the highest price among the Big Three memory makers. We believe Rubin variants equipped with Samsung’s HBM4 will be sold as a separate, higher-priced SKU compared with those using SK hynix or Micron memory. In effect, they would command a premium.

これ、どこだろう、Metaのネットワーキング？ ファラデー（智原）、サムスンおよびUMCと組み米国の2nmクラウドAI案件を受注 ASIC（特定用途向け集積回路）設計サービスのファラデー・テクノロジー（智原科技）の王國雍社長は本日、サムスン（Samsung）、UMC（聯華電子）、およびメモリーメーカーなどのパートナー企業と連携し、米系顧客から2nm（ナノメートル）プロセスを採用したクラウドAI（人工知能）案件の受注に成功したことを明らかにしました。契約総額は数千万米ドルに達し、同社史上最大規模のプロジェクトとなります。 ファラデーは本日、オンライン決算説明会を開催。王社長は、顧客からの受託設計（NRE）事業において先端プロセスで新たな進展があり、2nm GAA（全周囲ゲート）プロセスを用いたクラウドAI案件を獲得したと説明しました。同社にとって最も先端のプロセスであり、初の2nm GAA案件かつ最も複雑度が高いプロジェクトとなるため、極めて大きな意義を持つとしています。 王社長によると、顧客は当初4nmプロセスの採用を予定していたものの、製品ライフサイクルの延長を考慮して2nmへの変更を決定しました。本案件の総額は数千万米ドル規模で、2027年上半期に最初の売上が計上される見込みであり、その後は進捗に応じて順次計上されます。ファラデーにとっては過去最大規模の金額となります。 また王社長は、設計力および全体を取りまとめる統括・調整能力こそが2nm案件を獲得できた決定打であると述べました。本案件ではサムスンのファウンドリを採用し、さらにUMCやメモリーメーカーなどのパートナーとも協力します。 ファラデーの第3四半期業績は、量産事業が予想を上回ったことに加え、IP（半導体設計資産）事業が過去最高を記録したことから、第3四半期の売上高は前四半期比10.6%増の36億6,400万台湾元へと拡大し、同期としての過去最高を更新しました。 一方、製品構成の変化により利益率の低い量産事業の比率が高まったため、第3四半期の売上総利益率（粗利率）は前四半期比2.7ポイント低下の42.5%、営業利益は20.8%減の2億1,400万台湾元となりました。ただし、営業外の投資評価益の寄与により、親会社株主に帰属する純利益は40.8%増の2億7,900万台湾元、1株当たり利益（EPS）は1.07台湾元となりました。 今後の見通しについて同社は、第4四半期もIP事業が過去最高を更新する勢いで成長を続け、NRE事業も大幅に伸長する一方、量産事業は減少する可能性があると予想しています。第4四半期全体の売上高は第3四半期並みで推移し、粗利率は約45%を見込んでいます。 王社長は、2027年の売上高は2桁成長を遂げる見通しであり、IP、NRE、量産の主要3事業すべてで2027年に増収が見込めるとしています。

This is a good example why I continued to use cell level density but not block level density. Because when you want to use block level density compared different node, especially cross foundry comparison, too many detail you need to be considered. Like 18A vs N2 case, some people may say 18A has BSPDN so you should considered the block level density gain by BSPDN. Yes, because BSPDN move some metal layer to backside, so some dummy metal can also be placed and shared the backside space, so your device metal routine resource increase and block density may gain in some case. Actually, this block level density gain number by BSPDN is floating. Some case especially you use larger amount of HP/ UHP cell with dense power grid, this number can enlarge to ~20%. But in most case, a ~10% gain in area will be mentioned and estimated. However, if you want to compared the block level density, then many design rule detailed and DTCO you must considered. Like N2 offer NanoFlex that providing short-tall cell abutment that could yield in 15% performance gain under same area or translate to x% area gain under same performance, and 18A do not offer this DTCO until 14A. So how do you compared these block level density gain? Dummy rule constrained or dummy area reduction is another example, like Xiaomi claim 5% block level density gain by scrub line area reduction with O3 chip compared to O1 chip. So how can you confirm to add these extra 10% block level density gain by BSPDN on 18A but not considered the DTCO area gain on N2? Hence this ~10% density gain is only suit for same foundry comparison with FSPDN vs BSPDN in some applications. ( andto be mentioned, HD cell gain from BSPDN is much smaller than HP cell). So this is why I only use cell level density to compared the different node.

Yes, BSPDN could gain ~10% block level density over FSPDN. Actually, this number is floating. Some case especially you use larger amount of HP/ UHP cell with dense power grid, this number can enlarge to 20%. But in most case, a ~10% gain in area will be mentioned and estimated. But this is only suit for same foundry comparison with FSPDN vs BSPDN. If you truely want to compare the block level density, then many detailed design rule flexibility and DTCO you need to be considered. Like N2 has short-tall cell offering which could gain extra PPA no matter for 15% performance gain on same area or transfer to same performance but x% area gain, and 18A do not offer this short-tall cell design until 14A. So how do you compared these block level density gain across different foundry?

SemiAnalysis’s Dylan Patel, in a conversation with Stacy Rasgon and Austin Lyons: “Anthropic has already begun developing its own custom chip and is aiming to do it in half the time it took OpenAI.”