🤝 @dMatrix_AI is adopting NVIDIA NVLink Fusion to connect its next-generation Raptor XPUs with NVIDIA AI infrastructure, joining a growing ecosystem of partners using our rack-scale architecture for AI factory-scale deployment. By bringing together NVIDIA NVLink scale-up, Spectrum-X scale-out networking and the NVIDIA MGX rack architecture, d-Matrix can build specialized inference systems on a proven, rack-scale foundation spanning compute, racks, networking and software. Learn more:

A note from our co-founder and CEO @zainasgar on Gimlet Labs' $300M Series B. This milestone belongs to the team building Gimlet Labs. We’re hiring across the company as we scale our multi-silicon inference cloud. If you want to tackle some of AI infrastructure’s hardest problems and help build for the agentic era, join us:

At Ray Summit this week? Join Parasail + @dMatrix_AI on Wednesday for AI Infrastructure, After Hours, a VIP happy hour for founders and engineers working across AI and inference. Drinks, light bites, useful shop talk. 5:30–7:30 PM in SF. RSVP:

Hot Chips 3D DRAM session: D-Matrix says its 3D DRAM moves data 6-to-7x more efficiently than HBM4 on measured silicon "On comparing with HBM4, like we heard in the morning, we can get about 2.4 picojoules per bit energy efficiency on HBM4 of moving data into the base die." "There's obviously additional energy burned to move the data sideways into the GPU, which is not counted here." "But using this face-to-face stacking with 3D DRAM, we are able to reduce that energy to 0.37 picojoules per bit. This is a measured number." "And so this gives us, you know, 6 to 7X energy efficiency." "So for the same amount of power you can drive the bandwidth up, and so we were able to drive the bandwidth up here to 100 terabytes per second." "And in this construction it's a single-high stack, and like I showed, even with 32 gigabytes of memory capacity we are able to solve SOTA models in a scale-up network." "So no bits are wasted."