TSMC VP Jun He, ‘The CoWoS guy’ head of advanced packaging technology, media report: -“very close” to meeting CoWoS demand, but not yet -10 advanced packaging plants now -CoWoS capacity doubled each of last 3-years -5.5x reticle size CoWoS in mass production with over 98% yields on multiple AI client products -14x reticle size CoWoS out by 2029 -TSMC to introduce new technology every year -SoIC 6-micron hybrid bonding pitch in mass production last year, will shrink to 4.5 micron by 2029, for A14 chip stacking. SoIC offers 50x interconnect density, 5x energy efficiency -Beyond 3x Reticle size, quality of all components must beat automotive-grade to keep failure rates low -Bottlenecks: ABF substrate shortages will be 2nd to memory in coming years. Companies are sourcing substrates from multiple suppliers now to keep up, and variations in thermal & mechanical properties are an issue. -Boosting Yields via Chiplet ‘Smart Matchmaking’: Reclaims dies that might otherwise be scrapped by matching with ones that ensure consistent performance. -Interposers: Evolving from connection layer to also house voltage regulators, capacitors, and Silicon Photonics. -Shift to Parallel Development: Customer chips now enter fabs before testing finalized; suppliers must station R&D teams near TSMC fabs to make real-time fixes during mass production. -Early System Specifications: TSMC to publish system guidelines 6 quarters before mass production so clients and suppliers can align on thermal, mechanical, power requirements (STCO). $TSM $NVDA $AMD $AMZN $GOOGL $AVGO $MSFT $META #semiconductors#