"Don't let ambition become self-sacrifice” Astronaut @Astro_Soichi on what space taught him about ambition, limits, and readjusting to life on the ground - which he says was the hardest part. As an overachiever, he says, you push to do more than you can handle. Eventually something gives, be it your health, your relationships, or your daily life. His advice to the next generation: don't let that something be you. #AMNC26# #IdeasOnTheMove#

- Global Unichip Corp. (GUC, has announced a 16 Gbps HBM4E PHY and Controller IP on TSMC N2P, targeting next-generation AI ASICs with support for CoWoS and 3D SoIC architectures. - Importantly, the 2nm designation refers to the ASIC-side HBM PHY and Controller IP implemented on TSMC N2P, not the DRAM process used to manufacture the HBM4E memory itself. - GUC says the HBM4E PHY and Controller design has been finalized and has already been adopted by a customer's AI ASIC, although the customer has not been disclosed. - The previous 12 Gbps HBM4 PHY and Controller on TSMC N3P is already silicon-proven, with GUC now extending the platform to 16 Gbps HBM4E. - GUC CTO Igor Elkanovich says its HBM4E solution delivers 3.3x bandwidth, 2.6x area efficiency, and 1.4x power efficiency versus HBM3E, based on GUC's IP comparison. - The platform goes beyond conventional CoWoS HBM connectivity by supporting a face-up HBM PHY for TSMC SoIC-X, including TSVs for I/O, power, ground, and feedthrough power delivery to logic dies stacked above the PHY. - GUC is positioning HBM4E together with face-up UCIe and GLink-3D as a broader 3D ASIC interface platform, enabling integration across HBM, chiplets, and vertically stacked logic. - The timing is notable because SK hynix announced in June 2026 that it had shipped 12-layer HBM4E samples operating at up to 16 Gbps per pin to major customers, meaning both the memory and ASIC/IP ecosystems are now preparing for the same performance generation.

# 3D Packaging & **Onto Innovation (ONTO TP $397) Note * **Outlook:** 2026 revenue guided at **$1.3bn**; capacity supports **$2bn** by 2027. ### **3D Packaging Trend** We expect the shift to 3D for Nvidia Feynman, AWS Trainium, and Google V9 (Broadcom). * **Capacity Surge:** We forecast TSMC SoIC capacity to be 15KPM and 35KPM by end of 2026 and 2027. * **Tools:** **G5/3Di** tool shipments expected to jump from ~30 units in 2026 to >100 units in 2027. #ONTO#

$MU $SKHY $DRAM $NVDA $LITE AI is still diapers According to $TSM's HPC roadmap (SEMI Taiwan today), AI compute demand growing 5x/year, creating a "compute wall" and "memory bandwidth wall." TSMC's answer is heterogeneous integration across logic, 3D packaging, and silicon photonics. Logic process: Moving fully to nanosheet architecture. After N2 and A16, TSMC targets A14 (angstrom class) in 2028 to 2029. 3D stacking (SoIC): In production since 2023 with 56x the interconnect density of traditional 2.5D. Roadmap is N2P on N3P in 2026, then A14 on A14 in 2029, shrinking bump pitch to 4.5 microns. CoWoS packaging: 5.5x reticle size in 2026 (supporting 12 HBM3E/4 stacks, yield over 98%), 9.5x reticle by 2028, and over 14x reticle with 24 HBM stacks by 2029. Combined system compute: TSMC projects SoIC plus CoWoS integration will deliver 50x the 2024 compute level by 2029. HBM4 and the memory wall: Interface bandwidth doubles to 2048 bit. Base die built on N12, cutting power over 45% and boosting bandwidth 2.5x, with a future move to N3 for further gains. Overall memory bandwidth is projected to grow 34.6x by 2029. COUPE (silicon photonics): 3D stacks the electronic die directly onto the photonic die via SoIC, with 2 to 4 micron bond pitch. At 112Gbps, transmission loss is just 0.06dB versus 1.38dB for microbumps, cutting latency to 10 to 20 nanoseconds. First 200Gbps micro-ring modulator (0.5 Tbps/mm density) ships in 2026, scaling to 4 Tbps/mm by 2030. Design enablement: TSMC is building an optical PDK for electro-optic co-simulation plus automated DRC/LVS/thermal flows to speed 3D IC and photonic design.

Semianalysis: "Market chatter suggests $GOOG is working with $AMD on a TPU project in the v10 generation. AMD’s involvement would be the first real involvement in a custom AI ASIC project, despite having a custom silicon team. AMD has strong IP especially in advanced packaging and SoIC. Additionally, CPU IP could also be a draw given Google and its customers are pushing for TPUs with on-package CPU cores for RL workloads." $AVGO: "We are seeing lower TPU output in 2H26 than previous expectations...For 2027, we also see lower TPU output than our previous expectation of 6mn units of TPU 7 and TPU8i. This is driven by greater allocation towards other customers."

Nvidia’s next generation chip platform, Feynman is ahead of schedule, will use TSMC’s A16 process, and CPO (co-packaged optics), DigiTimes reports, with TSMC full speed ahead to meet 2028 mass production. -Nvidia is rapidly shifting its supply chain to put Feynman out in the 2nd half of 2028 -Feynman uses 3D chiplets, SoIC packaging and CPO. (Silicon-on-Integrated-Chips). -Total rack bandwidth for Feynman to hit 1,000 TB/s versus 260 TB/s for Rubin and 520 TB/s for Rubin Ultra, making CPO vital. -TSMC construction at advanced packaging plants AP7 in Chiayi and AP8 in Tainan are ahead of schedule, and accelerating -SoIC, CoWoS-L and CoPoS are all being pulled forward -SoIC capacity seen at 50,000 wafers-per-month (wpm) by end-2027, vs end-2026's 20,000wpm $NVDA $TSM #semiconductors#

If $AMD wins, $TSM Advanced Foundry Process and Advanced Packaging win. Also a win for $DRAM as it packs 50% more memory than competitors. “AMD unveils its sixth-generation EPYC 9006 server CPU and Instinct MI455X GPU, expanding its AI portfolio across agentic AI, cloud computing, enterprise, and high-performance computing (HPC). … the move is expected to drive demand for TSMC’s advanced packaging technologies, including CoWoS-L and SoIC.” “AMD notes that the EPYC Venice processor has entered volume production on TSMC’s advanced 2nm process technology, while the MI455X is built using TSMC 2nm and 3nm FinFET technologies.” “The MI455X integrates 320 billion transistors using multiple advanced packaging technologies. Four Accelerator Complex Dies (XCDs) are hybrid-bonded onto each Fabric and Cache Die (FCD), while the two FCDs are interconnected with 12 HBM4 stacks, two I/O dies, and each other using TSMC’s CoWoS-L packaging technology.” “Some high-end EPYC Venice models are reportedly expected to adopt TSMC’s CoWoS-L packaging and be manufactured at TSMC’s Kaohsiung Fab 22, with production expected to ramp in the second half of 2026 to support growing demand for agentic AI servers.” “CoWoS-L capacity remains tight. … some Chip-on-Wafer (CoW) orders are expected to be outsourced to ASE, while TSMC and OSAT providers continue expanding CoWoS capacity with visibility extending through 2027 and 2028.” “AMD’s MI450, MI455X, and future AI chips are expected to boost SoIC (System-on-Integrated-Chips) demand. Institutional investors … estimate that TSMC’s SoIC capacity will reach 15,000–20,000 wafers per month by the end of 2026, before doubling again by the end of 2027.” “AMD’s Instinct MI455X adopts HBM4 memory, increasing capacity by 50% from 288GB of HBM3E on the MI350 series to 432GB. Memory bandwidth also rises to 22.3 TB/s, up 2.8× from 8 TB/s on its predecessor.” “The MI455X delivers up to 40 PFLOPs of FP4 and 20 PFLOPs of FP8 performance—roughly doubling the compute capability of the MI350 series. By comparison, Nvidia’s Rubin GPU provides 50 PFLOPs of FP4 and 17.5 PFLOPs of FP8 performance.” (Nvidia Rubin is noted with 288GB HBM4 and up to 22 TB/s bandwidth.)

336K AERO Buyback ✈️ The Aerodrome PGF has just executed a 336K $AERO buyback, leveraging its market-aware strategy. To date, nearly 200M $AERO has been bought back and locked via the PGF, Flight School, Relay and other efforts.

Do you see that tiny glowing streak? That's the SpaceX Crew Dragon heading back to Earth in the early hours of May 2, 2021—5 years ago this week. Astronauts on the International @Space_Station saw the Crew Dragon blazing through Earth's atmosphere, as NASA astronauts Mike Hopkins, Victor Glover and Shannon Walker, and JAXA astronaut Soichi Noguchi returned home. Crew-1 safely splashed down off the coast of Florida, completing their 167-day mission on the space station, and the first operational mission of NASA's Commercial Crew Program.