William David
@WDChokepoint
Physical reality constrains digital ambition. That gap is the investment thesis. Critical minerals. Semiconductors. Energy. The constraint always moves upstream
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@damnang2 Points 3 and 5 are the same point. Samsung does CPO with its own foundry and builds its own CXL controller. Its custom HBM logic die is going in-house at 2nm while SK hynix’s HBM4 base die sits at TSMC. The divergence on that roadmap isn’t memory. It’s who owns the logic.
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Quanta’s new guidance floor is above their old ceiling. Not a beat, a full range shift. Backlog: $53.4B, up 49% year over year. This is the company that builds the wires and substations. The constraint was never just chips.
$PWR #GRID# #infrastructure#
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A memory chip stack with a 99% success rate on every connection still only has an 86% chance of working at 16 layers. Not because anything failed - because you multiplied 99% by itself sixteen times. One reason only three companies make this chip at scale.
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DRAM contract prices didn't move today. They're still rising into Q3. Markets price narratives. Supply chains price physics.
Kimi K3’s weights are live - 2.8 trillion parameters, only about 50 billion active per token. That efficiency is real. But the other 2.75 trillion still have to sit somewhere the moment someone self-hosts it. Sparse compute doesn’t mean sparse memory.
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The interconnect point is the one that lands - splitting memory into tiers doesn’t just relocate the shortage, it creates a new one at the seams. That’s a cost nobody’s pricing yet.
I think the answer would be both.
Easier to engineer, harder to supply.Easier because designers can now place each byte in the cheapest memory that meets its latency budget.
That relieves the scarcest tier, HBM.Harder because demand doesn't shrink, it just spreads across tiers sharing the same fab capacity.
Helios is the proof: AMD planned 1TB of LPDDR per GPU as a relief valve, then deleted it because that memory got tight too. Shortages leak across tiers.
And the hidden tax: once memory splits into pools, the wires between pools become the new bill.
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3.1 GW of data center load vanished in 30 seconds this week - one downed transmission line, an 11-minute voltage spike from DC to Chicago. Bypass power protects the facility. It doesn't make the facility invisible to the grid.
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A transmission fault outside DC on 25 July dropped 3.1 GW of AIDC load in roughly 30 sec. The resulting 3.49 GW surplus drove a voltage spike across the entire PJM system, from Northern Virginia to Chicago, taking 11 minutes to clear.
These facilities act as synchronized, low-inertia loads. Their protective schemes trip nearly together, turning a local contingency into a regional frequency /voltage event. As AIDCs approach a projected 24% of PJM demand by 2040, coincident disconnects become a systemic risk rather than an edge case.
On-site storage sized for full-load bridging, plus inverter controls that provide synthetic inertia + ride-through, can absorb the step change w/out cascading further trips. The episode shows that compute density & grid dynamics now require joint design, not sequential hardening - our focus 🙌
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Homer City, PA had America's largest coal plant. Now it's the largest gas plant instead, powering a data center on the same lines.
The turbines took three years to get.
That's this week's real AI bottleneck. Six companies sit inside that gap:
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Nvidia's $500B SK Hynix deal isn't really about the deal size. It's compute, memory, and power all in one commitment - a 2 gigawatt data center means Nvidia is now underwriting grid capacity just to secure memory it can't get elsewhere.
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