Theres a difference between sophistication and the asthetic of sophistication. Most people attend cultured events and seminars not out of genuine curiosity, but for signaling purposes to look cultured. There are a few dead giveaways people do this, such as asking at the beginning of an event, "what other events do you go to" and if they immediately lead with where else they've been. But not everyone does this, and those are often the quiet ones off to the side, often fed up with performative sophistication. Just tonight, I was just describing my website to a non tech person who was genuinely curious about how tokens flow through AI infrastructure. I kept the conversation at a very high level since he didn't have a technical background and was still able to share trends like optical for improving AI compute due to copper limits. I totally understand most people won't have a PhD background in most topics. However, I think grappling with discomfort goes a long a way to making yourself increasingly receptive to understanding more complex topics and cultivating your taste.

An entire generation of tech talent chose software because it operated on a quiet status hierarchy over hardware. Software was popular because it operated on an ultimate abstraction: comfort. Meanwhile, the hardware stack—OSAT packaging in Malaysia, cleanrooms in Taiwan, signal integrity, and power delivery—was treated as low-margin "dirty work." For decades, the tech industry treated hardware like an afterthought and built a whole ecosystem with this attitude. Now, with AI compute, the tides have turned: HW companies are capturing most of the value. Big Tech executives who ignored hardware physics for twenty years are now getting furious when advanced packaging lines don’t follow the same trend as SW release cycles. Many wonder why the workforce is burnt out. The bottleneck now flows through hardware.

"Silicon Co-Design" went from 1k to 10k followers on X in a day and #6# rising in technology on Substack! I cover the technical foundations of the underlying subsystems of AI Infra from the bottom-up, including advanced packaging, high speed optical communications, mixed-signal, power, and memory. Up until this point, I self-funded this self-education journey by travelling to flagship technical conferences (ISSCC, DesignCon, APEC, ECTC, DAC, and Hot Chips), sitting in rooms full of domain-specific experts, walking the expo floors, and learning from grad students at poster sessions. It has been a humbling journey for sure and it has not been easy to walk into these conferences without an affiliation and not feel any sense of reward. I want to thank everyone who has been with me from the beginning. Thanks @vikramskr for getting the ground running with your research and @bookwormengr on X for recently reposting my OpenAI's Jalapeno post that got me from 1k to 10k X followers.

An advanced system architecture breakdown of OpenAI’s Jalapeno inference accelerator that goes beyond raw FLOPs and into the surrounding network architecture and how AI actually added value:

A lot of CPO performance can be left on the table if the high-speed 224Gb/s+ SerDes bottlenecks data throughout in the overall electrical - optical data link. Most people hyperfocus on analyzing the performance of CPO because its components can be easily analyzed individually: EIC, PIC, laser source, modulator scheme, bonding mechanism, etc. However, high speed SerDes is often treated as a "black box" by outsiders. Inside that black box, SerDes increasingly relies on sophisticated IP blocks in specific process nodes such as ADCs, PLLs, and DSP blocks. In this post I break down a modern high-speed SerDes architecture from ISSCC and key tutorial papers. This article is intended for designers working on SerDes blocks who often don't have system context, as well as outsiders interested in learning more about SerDes from first principles.

AI has actually made the lives of chip designers building AI accelerators harder, not easier. On the design side, AI does offer some productivity benefits for chip designers, such as vibe coding RTL. However, quite paradoxically, silicon for AI applications requires increasingly complex architectures and compute requirements. There are also several other problems chip designers have to deal with, including: - Verification, which has historically been the most labor-intensive step in chip design - Multiphysics challenges with off-chip thermal/SI/PI/packaging - Late-stage firefighting in power closure due to bursty, unpredictable LLM workloads in systolic arrays I went to @DACconference, the heart of design automation for chips, and noticed that most experienced silicon engineers do not completely trust AI to design chips quite yet. In my latest deep-dive post, I cover these issues so that a broad audience can understand why from first principles.