At #HotChips2026#, d-Matrix is presenting Raptor™, our 3D DRAM architecture built for the growing memory demands of AI inference. Raptor brings memory closer to compute, delivering massive bandwidth with significantly lower I/O energy than HBM. @ServeTheHome goes inside the architecture and the work behind Raptor: #AIInference# #AIInfrastructure# #3DDRAM# #dMatrix#

$MU $SKHY Memory Innovation Is Just Getting Started. 3D DRAM Incoming. "SK hynix is reportedly stepping up development of 3D $DRAM, a next-generation memory technology for on-device AI. … the company has reportedly begun recruiting 3D-Stacked DRAM-on-Logic Design Engineers through its U.S. subsidiary in San Jose, California. SK hynix is also said to have partnered with a specific customer to develop applications for the technology.” “SK hynix President and Chief Development Officer (CDO) Hyun Ahn said AI development is increasingly constrained by memory bottlenecks, requiring new memory architectures beyond incremental improvements. He said the company is working with TSMC to apply its advanced logic process to HBM4 base dies, with plans to expand the technology to High Bandwidth Flash (HBF) and 3D-Stacked DRAM-on-Logic to further integrate memory and logic for higher performance and power efficiency.” It's not just SK Hynix. I've talked to my buddies in the industry. Micron and Samsung are actively R&Ding on 3D DRAM. This product is going to be perfect for AI Inference.

$NVDA is turning MGX into a broader inference platform by adding d-Matrix Raptor for frontier models that need far more memory than SRAM can support. Groq covers ultra-fast SRAM inference while Raptor brings 2.3TB of 3D-DRAM per rack through the same NVLink ecosystem.

At #HotChips2026#, d-Matrix shared a closer look at Raptor, our 3D DRAM architecture designed to bring memory and compute closer together, delivering 100+ TB/s of bandwidth with significantly greater energy efficiency. @wccftech takes a deeper look at the architecture and what it could mean for scaling AI inference. Read more: #AI# #AIInfrastructure# #Inference# #Semiconductors#

Every accelerator company, and I mean every accelerator company, is likely going to do some variant of 3D DRAM or the “zHBM” which were both discussed at HotChips today. The larger companies will probably run (are running) parallel programs, but these two memory variants probably co-exist for a long time. Each has distinct advantages.

FORMER TESLA DOJO TEAM’S AI CHIP STARTUP NEARS $10B VALUATION DensityAI, founded just a year ago by former leaders of Tesla’s Dojo supercomputer program, is in advanced talks to raise hundreds of millions of dollars at a ~$10B valuation, per The Information. The startup has told investors that AWS has agreed to buy its future chips if they meet certain performance requirements. DensityAI is developing AI inference chips using 3D DRAM stacking, placing memory directly above compute to reduce data movement and potentially improve speed and energy efficiency. Andreessen Horowitz is reportedly in talks to lead the round.

EX-TESLA DOJO FOUNDERS’ AI CHIP STARTUP NEARS $10B VALUATION DensityAI, founded just a year ago by former leaders of Tesla’s Dojo supercomputer team, is in advanced talks to raise 100s of millions of dollars at a $10B valuation, per The Information. The startup has told investors it secured an agreement under which AWS would buy its future chips if they meet certain performance requirements. DensityAI is developing AI inference chips using 3D DRAM stacking, placing memory directly above compute to reduce data movement and potentially improve speed and energy efficiency. Andreessen Horowitz has been in talks to lead the round. Source: The Information

UBS Hot Chips 2026- Model size + KV cache keep going up. Roadmaps are now capacity, bandwidth, and scale-up — not peak FLOPS. $GOOG TPU 8i (inference, 2-die) is a memory-bandwidth chip: 384MB on-die SRAM, 288GB HBM3E, 19.2Tb/s inter-chip. Built because reasoning / MoE / agentic decode is now more memory-bound than training. TPU 8t ( $AVGO, training): 9,600 chips/Superpod, 121 EF FP4, 2PB shared HBM. Different product. Training and inference silicon have diverged enough to justify two architectures. Same conference, same bottleneck everywhere else: Samsung LPDDR5X-PIM: MAC inside the DRAM banks. 614GB/s PIM BW (8x LPDDR5X), ~3x Llama-3.1-8B tokens. Cheap inference vs HBM. CXL pooling (Samsung demo): 3.35x LLM decode at 100K context. d-Matrix 3D-DRAM: META engineer on stage. 32GB/card, ~100TB/s, 1M-token context in a 72-card rack. LPX (Groq/$NVDA): no HBM at all. SRAM-only decode. LPX + Rubin ~3-5x on long-context agentic. $CBRS CS-6: 3D DRAM on wafer-scale SRAM. ~2028. Net: TPU 8i is Google saying inference is a memory-movement problem. PIM / CXL / 3D-DRAM / SRAM decode are everyone else saying the same thing. AVGO still has the training Superpod. The duration is the memory stack sitting under both.

Qualcomm working with CXMT for custom memory has been making the rounds. Here's what's missing from the coverage: 1. This refers to Qualcomm working with GigaDevice on a discrete smartphone NPU, targeting Chinese smartphone brands. 2. Shipments are expected in late 2026 or early 2027, aimed at devices priced above RMB 4,000–4,500. 3. The NPU delivers ~40 TOPS of compute and is paired with 4GB of customized 3D DRAM, manufactured by CXMT. 4. It delivers higher memory bandwidth than LPDDR5X, with TSV and Hybrid Bonding stacking. 5. Shipment outlook and design wins are now below initial 1H25 expectations, mainly due to: (1) rising memory prices driving up NPU costs; (2) on-device AI use cases and business models still lacking clarity to date.