Google is testing $INTC EMIB-T. Why is it also talking to $TSM? Because if you need millions of TPUs, you want a backup before production starts, not after something goes wrong. Morgan Stanley expects Intel’s EMIB-T capacity to grow from 5k to 45k wafer equivalents per month by 2028. That’s a serious ramp. But its report also shows the risk: it estimates enough EMIB-T substrates for roughly 2 million Humufish chips, while its shipment case assumes 2.5 million from Intel plus another 0.5 million using TSMC’s CoWoS-L. That extra CoWoS-L capacity could help Google hit its target if Intel runs short. I don’t read it as Google deciding to split production between the two forever. CoWoS-L costs more, and making the same chip work with both packaging methods takes extra design work. IMO Google is keeping its options open while it learns what EMIB-T can actually deliver at scale. If Intel gets the yields and capacity right, I think it could win most of the Humufish packaging work. Intel doesn’t need to replace CoWoS across the industry for this to matter. It needs to show that Google can count on it.

Why did Intel abandon EMIB for their 2027 Diamond Rapids CPU? Uniform Memory Access. All CPU cores in each CBB can access all 16 memory channels with a single hop. UCIe-S through the substrate was required to route signals underneath the near-IMH to the far-IMH with about 30mm of reach to achieve this. In contrast AMD's Venice is a NUMA design. Half the memory channels are on a remote-IOD that require an extra hop for the cores in the CCD to access vs memory channels in the local-IOD. As a bonus, Intel also saves on packaging cost without having to use EMIB, freeing up advanced packaging capacity for their external foundry customers

📈 #Intel#'s #EMIB-T# is gaining momentum. #PSMC# reportedly secures exclusive supply of key silicon capacitors, while #UMC# sees strong silicon bridge demand. How far can the ecosystem expand? 💡More: 🔗

Intel’s EMIB Packaging Is Growing Rapidly — Silicon Capacitors Are Taking Off Too Silicon capacitors are poised for explosive growth in the AI semiconductor space. Intel has been found to be planning a large-scale adoption of silicon capacitors starting next year, in order to enhance the performance of its in-house 2.5D packaging technology, “EMIB.” The most clearly visible source of demand is Google. Google plans to launch its next-generation AI accelerator, “v8e,” in the second half of next year, and has adopted an EMIB substrate with embedded silicon capacitors for that chip. With other Big Tech companies such as Amazon also currently applying EMIB, analysts say demand could increase sharply. According to industry sources on the 27th, Intel plans to apply silicon capacitors to its 2.5D packaging starting next year. Intel Adopts “Silicon Capacitors” for 2.5D Packaging… Google AI Chip Gets First Application 2.5D is an advanced packaging technology that inserts a thin-film interposer between the semiconductor and the substrate. Because it can connect circuits at higher density compared with conventional packaging that uses only a substrate, demand is rising in the AI and HPC fields. To improve cost efficiency in 2.5D packaging, Intel devised its own technology called EMIB. Rather than using a broad, spread-out interposer, EMIB connects chip to chip using a small silicon bridge. Since bridges only need to be placed where chip-to-chip connections are required, chips can be arranged more flexibly and efficiently. Recently, EMIB has been drawing attention as an alternative to TSMC, which had been leading the existing 2.5D packaging market. This is because TSMC’s 2.5D packaging capacity is suffering from a supply shortage amid the rapid development of the AI industry. Indeed, global Big Tech player Google is also paying attention to EMIB. Google has decided to adopt EMIB for its in-house AI semiconductor “v8e,” which it plans to launch in the second half of next year. Under this structure, TSMC handles chip mass production, MediaTek handles design and manufacturing support, and Intel handles packaging. However, there have been concerns that EMIB is gradually showing limitations in providing stable power supply for AI semiconductors, which consume large amounts of power. Accordingly, Intel plans to introduce new technologies such as silicon capacitors and through-silicon vias (TSV) to ensure stable packaging for the v8e. A capacitor is a component that stores and releases electricity in an electronic circuit. In the case of silicon capacitors, their resistance (ESL/ESR) is more than 100 times lower than that of conventional multilayer ceramic capacitors (MLCC), minimizing the signal loss that occurs in high-performance semiconductors. They can also be designed in an ultra-thin structure based on a silicon wafer, enabling high-density integration. A semiconductor industry official explained, “Because the voltage drop (the phenomenon of voltage decreasing) that occurs in the high-frequency region within AI chips is difficult to solve with MLCC, we understand that Intel is adopting silicon capacitors as a solution,” adding, “The relevant supply chain is now in place, and mass production is set to begin in earnest next year.” EMIB-T Is Already on a Growth Trajectory — The Related Ecosystem and Market Are Expanding Together Intel has also inserted TSVs, which serve as power-delivery channels, into the silicon bridge. The key point is that by using TSVs to shorten the power-delivery path between the substrate and the chip, Intel has improved power efficiency and signal integrity. Intel calls this “EMIB-T.” The industry expects the EMIB-T and silicon capacitor markets to grow rapidly. This is because Japan’s Ibiden — one of the major companies that mass-produces semiconductor substrates for EMIB-T — is aggressively pursuing capital investment. Previously, Ibiden had planned to build its Kawashima (Gama) plant in Gifu Prefecture as a substrate plant for Intel CPUs. However, it postponed that schedule and decided in the first half of this year to officially convert the Gama plant into a mass-production line for EMIB-T substrates. The investment is 220 billion yen (about KRW 2.1 trillion). In its recent earnings announcement, Ibiden stated, “Operation of the Gama plant will begin in 2027 and enter full-scale mass production in 2028,” adding, “EMIB-T substrate capacity is currently far short of demand. However, adding further capacity is quite difficult, so we are discussing options with our customers.” A semiconductor industry official explained, “Ibiden’s EMIB-T-dedicated line is being built with most of the investment coming from customers such as Google, Amazon, and Intel,” adding, “This demonstrates that AI semiconductors based on EMIB-T will grow significantly going forward, and silicon capacitors are likely to expand alongside them.”

Summary of MTK (2454) Update - 100% EMIB, 100% Share in v9 •Street-high TPU estimates → raised TP to NT$6,650 (from NT$6,420) •MTK fell 7% yesterday on noise around potential v8t delay, EMIB/substrate supply issues & v9 share-loss fears — we take the opposite view •v8t/Zebrafish remains intact; demand well above 2027 CoWoS allocation of 180k, suggesting extended life cycle vol. •EMIB-T / substrate yields & supply tracking better than expected, at ~50% currently. Yield rate in every stage in report •EMIB Substrate delivery in small-volume ~100k mid-2027 → mass-volume by 4Q27 💯 100% EMIB-T for v9 (Humufish, Triggerfish). on-track substrate yields + suppliers dedicated support. Also no reason for TSM to be a back-up or 2nd source. 💯 100% market share in v9 (Humufish for training, Triggerfish for inferencing). We expect no other v9/2nm projects during the time period •Life-cycle volume for v9 expected >5m (vs bears at >2m) •2nd ASIC project (likely SpaceX ASIC, not AI6) more visibility expected in 4Q26 •Datacenter ASIC forecast raised to NT$2.8bn / $18.6bn / NT$75.7bn •Near-term watch: engineering tape-out in Nov (passing bar not high; chipset testing at TSMC largely on track) •For v10: still expect MTK to win major SKU Icefish (AMD+MRVL or AVGO competing for Merope) #TPU# #MTK# #AVGO# #AMD# #MRVL# #v9# #intel# #intc#

Amazon is expected to use EMIB for both Tr3.5 and Tr4, so I was puzzled when Ibiden said EMIB-T wouldn’t come online in 2027. But today, sell-side said Tr3.5 will use EMIB-M, not EMIB-T. Now the whole mystery is solved. $INTC