📈 #Intel#'s #EMIB-T# is gaining momentum. #PSMC# reportedly secures exclusive supply of key silicon capacitors, while #UMC# sees strong silicon bridge demand. How far can the ecosystem expand? 💡More: 🔗

Some quick thoughts on Intel's EMIB-T packaging for the new 2H27 Google TPU (Humufish). Based on my industry checks: 【How to read EMIB-T's 90% yield?】 1. Given Intel's track record running EMIB in mass production, hitting 90% technology validation yield on EMIB-T (still under development) is a very positive but reasonable data point. 2. Intel benchmarks EMIB production/assembly yield against FCBGA. Industry FCBGA yield today is generally above 98%. 3. On yield, getting from 90% to 98% is harder than getting from project kickoff to 90%. And technology validation yield ≠ final production yield, especially with some Humufish specs still unfinalized. So long-term, I'm positive on Intel's advanced packaging story. Near to mid-term, I'm staying cautious on how they get there. 【From 90% to 98%. Looks like just a few points. Does Google care? Absolutely】 1. Google recently asked TSMC how much it could save by placing wafer orders for Humufish's main compute die (designed in-house by Google) directly, rather than routing them through MediaTek. 2. Google and MediaTek have run a semi-COT model since day one (8t). MediaTek's mark-up sits mostly on the parts it designs itself, so whether Google places the wafer orders for main compute die directly isn't a key swing factor for MediaTek's earnings trajectory. 3. But Google even probing whether it can squeeze out the pass-through mark-up on wafer orders tells you something: Google has shifted from easygoing buyer to hard-nosed on cost. The reason is simple: to take on Nvidia head-on, cost is Google's edge, which makes EMIB-T production yield Google's problem to solve. For context, TSMC's yield target on 5.5-reticle CoWoS in 2026 also starts at 98%. 【TSMC's position】 1. My understanding is TSMC is still working out how much advanced-node capacity to allocate to Humufish in 2H27, for two reasons: (1) it still wants the back-end packaging orders, though looks unlikely for now, and that's by design on Google's part; and (2) it's still gauging actual back-end output from EMIB-T, to avoid misallocating scarce advanced-node capacity. 2. Humufish's effective back-end output hinges on both EMIB-T and substrates, and both need to be tracked together. 3. On the Humufish semi-COT model, TSMC also prefers MediaTek to place the wafer orders for the main compute die. Beyond the close working relationship, the key point is MediaTek is TSMC's third-largest advanced-node customer in 2025. If TPU orders shift, MediaTek's scale makes it a natural buffer for TSMC to rebalance its wafer allocation mix.

Intel’s EMIB Packaging Is Growing Rapidly — Silicon Capacitors Are Taking Off Too Silicon capacitors are poised for explosive growth in the AI semiconductor space. Intel has been found to be planning a large-scale adoption of silicon capacitors starting next year, in order to enhance the performance of its in-house 2.5D packaging technology, “EMIB.” The most clearly visible source of demand is Google. Google plans to launch its next-generation AI accelerator, “v8e,” in the second half of next year, and has adopted an EMIB substrate with embedded silicon capacitors for that chip. With other Big Tech companies such as Amazon also currently applying EMIB, analysts say demand could increase sharply. According to industry sources on the 27th, Intel plans to apply silicon capacitors to its 2.5D packaging starting next year. Intel Adopts “Silicon Capacitors” for 2.5D Packaging… Google AI Chip Gets First Application 2.5D is an advanced packaging technology that inserts a thin-film interposer between the semiconductor and the substrate. Because it can connect circuits at higher density compared with conventional packaging that uses only a substrate, demand is rising in the AI and HPC fields. To improve cost efficiency in 2.5D packaging, Intel devised its own technology called EMIB. Rather than using a broad, spread-out interposer, EMIB connects chip to chip using a small silicon bridge. Since bridges only need to be placed where chip-to-chip connections are required, chips can be arranged more flexibly and efficiently. Recently, EMIB has been drawing attention as an alternative to TSMC, which had been leading the existing 2.5D packaging market. This is because TSMC’s 2.5D packaging capacity is suffering from a supply shortage amid the rapid development of the AI industry. Indeed, global Big Tech player Google is also paying attention to EMIB. Google has decided to adopt EMIB for its in-house AI semiconductor “v8e,” which it plans to launch in the second half of next year. Under this structure, TSMC handles chip mass production, MediaTek handles design and manufacturing support, and Intel handles packaging. However, there have been concerns that EMIB is gradually showing limitations in providing stable power supply for AI semiconductors, which consume large amounts of power. Accordingly, Intel plans to introduce new technologies such as silicon capacitors and through-silicon vias (TSV) to ensure stable packaging for the v8e. A capacitor is a component that stores and releases electricity in an electronic circuit. In the case of silicon capacitors, their resistance (ESL/ESR) is more than 100 times lower than that of conventional multilayer ceramic capacitors (MLCC), minimizing the signal loss that occurs in high-performance semiconductors. They can also be designed in an ultra-thin structure based on a silicon wafer, enabling high-density integration. A semiconductor industry official explained, “Because the voltage drop (the phenomenon of voltage decreasing) that occurs in the high-frequency region within AI chips is difficult to solve with MLCC, we understand that Intel is adopting silicon capacitors as a solution,” adding, “The relevant supply chain is now in place, and mass production is set to begin in earnest next year.” EMIB-T Is Already on a Growth Trajectory — The Related Ecosystem and Market Are Expanding Together Intel has also inserted TSVs, which serve as power-delivery channels, into the silicon bridge. The key point is that by using TSVs to shorten the power-delivery path between the substrate and the chip, Intel has improved power efficiency and signal integrity. Intel calls this “EMIB-T.” The industry expects the EMIB-T and silicon capacitor markets to grow rapidly. This is because Japan’s Ibiden — one of the major companies that mass-produces semiconductor substrates for EMIB-T — is aggressively pursuing capital investment. Previously, Ibiden had planned to build its Kawashima (Gama) plant in Gifu Prefecture as a substrate plant for Intel CPUs. However, it postponed that schedule and decided in the first half of this year to officially convert the Gama plant into a mass-production line for EMIB-T substrates. The investment is 220 billion yen (about KRW 2.1 trillion). In its recent earnings announcement, Ibiden stated, “Operation of the Gama plant will begin in 2027 and enter full-scale mass production in 2028,” adding, “EMIB-T substrate capacity is currently far short of demand. However, adding further capacity is quite difficult, so we are discussing options with our customers.” A semiconductor industry official explained, “Ibiden’s EMIB-T-dedicated line is being built with most of the investment coming from customers such as Google, Amazon, and Intel,” adding, “This demonstrates that AI semiconductors based on EMIB-T will grow significantly going forward, and silicon capacitors are likely to expand alongside them.”

Ibiden (largest substrate supplier for intel EMIB) — earnings call Q&A Q) What is the development status and technical difficulty of EMIB-T, and when does mass production start? A) We understand that one or two competitors are also developing the relevant technology. Ibiden has largely completed the technology-establishment phase and is about to enter the yield-improvement phase ahead of full-scale mass production, which we believe puts us ahead of competitors. The technical difficulty lies in the bonding of the silicon bridge and in the core formation process. The Gama plant will be brought online in stages starting at the end of FY2027 and will contribute to earnings from FY2028. If demand materializes before then, we plan to accommodate it using existing facilities. ---------------------------------------- Reads like a de facto confirmation of 2028 EMIB-T ramp. $INTC

👀 #MediaTek# confirms its AI ASIC collaboration with #Intel’s# EMIB-T advanced packaging. The chipmaker is now pushing 400G SerDes IP to target next-gen ASIC opportunities, including reportedly #Google’s# TPU v10 and Meta’s custom AI chips.💡More: 🔗

Super excited to welcome my close friend Seok-Hee Lee back to Intel! @seokhee4 is a highly regarded semiconductor process integration expert and successful CEO (SK Hynix). Early in his career, he spent over 10 years at @intel, contributing to several critical Intel process technologies. He will now oversee our advanced packaging technology development and drive exciting new system integration projects! Advanced packaging and system integration are increasingly critical areas for Intel Foundry and for the future of computing. Seok-Hee will help Intel accelerate the ramp of our industry leading EMIB-T and HBI technologies. I look forward to partnering with him and have him rejoin Intel at this critical time!

$TSM $ASX $INTC "TSMC is facing a surge in AI chip orders using its advanced packaging technology, such as CoWoS, but competitors such as Intel are benefiting as the Taiwanese semiconductor powerhouse is unable to keep up with demand." "Leading this advanced packaging race is none other than TSMC, whose CoWoS (Chip-on-Wafer-on-Substrate) had a head start over the competition and has been the go-to choice for several years. As demand shoots through the roof, even the Taiwanese giant is facing the brunt of existing bottlenecks within the supply chain and is unable to meet demand." "Intel is aiming to become the 2nd largest advanced packaging provider with its EMIB technologies that are poised to offer several benefits over CoWoS. Furthermore, a wave of Taiwanese packaging and test companies, namely ASE, SPIL, Powertech, and KYEC, is also taking advantage of the situation as TSMC orders face a spill-over effect." "Reports indicate that Intel, with active support from the US government, is aggressively pursuing advanced packaging, and Taiwanese packaging and testing companies, including ASE, SPIL, Powertech, and KYEC, are also taking advantage of the spillover effect of orders." "We have already seen reports that NVIDIA will move advanced packaging orders to Intel for its next-gen Feynman GPUs. These are anticipated to utilize Chipzilla's improved EMIB technology."

Intel CEO Lip-Bu Tan sat down with CNBC’s Jim Cramer to talk about Apple; Intel 14A rivaling TSMC's top chip production technology; Shortages of CPUs and substrates; and the state of Intel's turnaround. How to know when Intel signs Apple or other foundry customers: Intel CEO Lip-Bu Tan: “Over time, the IP will be ready so we can serve some of these customers. I think the best indication, when you see I increase my capex, I’m putting money to buy equipment, that means I have real customers. That’s the discipline I have.” Intel 14A manufacturing process and EMIB-T advanced packaging: Intel CEO: “(A14) is 1.4nm, this is the most advanced. To be candid with you, in 2028 we will have risk production. 2029 will be volume production. It will be the same time as TSMC. So that is a major, major breakthrough, and I’m so excited. And we already have multiple customers engaged with us, and we have 0.5 PDK available.” Taking advantage of TSMC’s CoWoS shortage Intel CEO: “Our technology is called EMIB-T, this is the next generation of advanced packaging. We really have the best technology and now we are making sure we can bring it into volume production with reliable yield so the customer can count on us.” CEO: “You know, CoWoS…(TSMC) ran out of capacity, so in a way we’ve become in the unique position to support that and that’s something we are very excited (about).” Shortages of CPUs and Substrates CEO on the CPU shortage: “I’ll give you one example. I had one customer say Lip Bu, we gave you the forecast for this year, but we want to increase 3x, and I say I cannot do it overnight but give me a few quarters and I will catch up. So, I think this demand is not short term, it’s the next couple of years. It’s a great opportunity.” CEO: “Right now, as I mentioned, CPU is in high demand. And that’s good for me. I cannot even ship enough to the customer. It used to be the CPU to GPU ratio for training was 1-to-8. And now, because of inference and agentic AI, and more agents you have to manage, and orchestration, and reinforced learning, CPU is actually better, so that becomes 1-to-4 and 1-to-1 and some people even talk about 4-to1, and so that’s a huge opportunity to me to drive the CPU....” CEO on Substrates: “A couple of customers have prepaid for substrates, because the substrate supply chain is very tight – so I need to put up the money to secure this material…(and it shows) the commitment to me – so that’s very exciting.” Intel’s Turnaround CEO: “We used to have leadership in data center, and over the years we lost it…We made some big mistakes,” he said, adding he’s brought back some talent to refocus the product lines and that “Coral Rapids will have multi-threading, and will come out very strong.” CEO: “When I took over, the 18A yield was not good, so I had to ask some of the ecosystem partners to help me look at the data, see how to improve. The best practice is to see 7% or 8% yield improvement per month, and now I’m seeing it.” CEO: “The other part is supposed to be the yield performance, defect density, you know at the end of the year to see the target. Now I see that even before the end of the year – so that is very big encouragement for me and also that’s why Panther Lake can be shipped in volume now. And now some customers knock on my door and say Lip Bu, now we hear you are making great progress, can you now open up to outside customers? So that is very exciting. It’s a lot of hard work, it’s a lot of teamwork, it’s a lot of talent I’ve brought on board.” CEO: “In the past we made a lot of mistakes and now we correct the mistake and we’ve simplified the roadmap. By the way, from Day 1 I came on board as the CEO, I have all the engineers report to me so I have an understanding, hear from the customer, and know where are the mistakes.” Cramer: “They didn’t report to the previous CEO?” CEO: “No. And in a way, they had too many silos, too many people reporting…So I decided, the best thing is to really understand where the problem is, so I can focus on the engineering, how to redesign, simplify the product and then get the real killer products out.” Cramer asks about China, Taiwan and the importance of US manufacturing: CEO: “I was very glad for President Trump understanding the strategic importance for the United States to have (chip manufacturing supply chain) and their support is so valuable to me – it’s so critical for the country to have the technology, R&D development, manufacturing in the United States. That’s why I came back in, as a U.S. citizen – as a calling – to do that.” CEO: “From time to time I update President Trump and also (Sec.) Howard Lutnick and they are big supporters of me and we are delighted to have their support.” Going forward: CEO: “I recruited some key talent…and now, by the end of June, I will have my team, what I consider my team, so that we can work on the next 5-years, 10-years, how to become a different company. I call it the New Intel, work at the speed of light, work as a team to progress forward.” $INTC $TSM #Samsung# $UMC $GFS #semiconductors#

What's the next step change in chip packaging technology? @bubbleboi: "The main difference between EMIB and CoWoS is CoWoS relies on what we call silicon interposers. They're like these huge plates where you put the chips on, and you start etching channels in between through the interposers." "An effect of that is that heat dumps into the interposers, just like anyone knows when they heat up popcorn, things expand and contract, and this creates worse yield." "NVIDIA's already seen this. Part of the reason why Blackwell had trouble ramping was all thermals, the package warping. That's a huge issue." "I think even TSMC knows it's a huge issue because in their further along roadmap, they don't really plan on adopting that for much longer. They're now going to a more Intel style thing where you use little bridges... smaller pieces of silicon to connect just the relevant parts." "What that effectively does is cut your costs 'cause you're using way less silicon, the thermals, the communication, it's centralized in one area."