Not worried about OpenAI’s ARR. Approaching $50B at end September is net vs. gross. We also know OpenAI excludes cloud-partner revenue Anthropic counts so investors marked the number up to force comparison. Sales didn’t fall $20B and not to mention $50B is still ~2.5x the ~$20B run rate at EOY25 on the capacity that’s already online. $60B+ blended revenue per GW on 10-12 GW of dedicated inference is how you get to $600B+ combined lab ARR by EOY27. That capacity is NOT built yet. Zephyr is right, the next leg will absolutely be agents that stay on for weeks. Then Bel/model 3 class models taking a cut of global R&D spend. So no I’m not really worried about OpenAI ARR today. Demand hasn’t even neared what it will be for enterprise, SMBs, and the regular consumer.

Can someone explain how media headlines about OpenAI’s ~$50B ARR… (vs. ~$70B from incorrect accounting comparisons with Anthropic) Somehow ends a 3-5 year laser shortage with $AAOI or memory shortage with $MU? Hint: it doesn’t.

[EXCLUSIVE] SK HYNIX CONSIDERS INTEL FOR NEXT-GENERATION HBM BASE DIES SK hynix is moving to diversify the foundry suppliers for the base dies used in high-bandwidth memory (HBM), which is built by vertically stacking multiple memory dies. The company is reportedly considering outsourcing a portion of the base-die production for HBM4E, the seventh generation of HBM, to Intel Foundry. Until now, SK hynix has relied entirely on TSMC for outsourced base-die production. The move is seen as an effort to establish a multi-vendor foundry strategy, reducing supply-chain concentration on TSMC while also strengthening SK hynix’s bargaining power on pricing. According to industry sources on August 31, SK hynix is pursuing a plan under which base dies for HBM4E could be manufactured by both TSMC and Intel, potentially beginning as early as the HBM4E generation. The base die sits at the bottom of an HBM stack and functions as a controller chip that supports and manages the overall structure. It is also commonly referred to as a logic die. The base die is responsible for the high-speed interface that connects HBM with external processors such as GPUs and CPUs. Up through HBM3E, SK hynix manufactured its base dies using its own processes. However, as successive HBM generations have placed greater importance on the logic, control functionality, and performance of the base die, SK hynix began working with TSMC to manufacture base dies starting with HBM4. SK hynix’s HBM4 products currently in mass production use base dies manufactured on a TSMC 12nm-class process. The key issue is the cost burden associated with the base die. According to industry sources, the TSMC-produced base die used in HBM4 is estimated to cost three to four times as much as the core dies—the DRAM dies stacked above the base die that directly store data—which SK hynix manufactures using its 10nm-class fifth-generation 1b process. The base-die cost burden is expected to increase further with HBM4E. Because HBM products are heavily covered by long-term supply agreements (LTAs), it is also difficult for SK hynix to immediately pass higher foundry costs on to customers through higher product prices. For this reason, industry observers believe that if Intel ultimately joins SK hynix’s base-die supply chain, the company would gain additional options in terms of both cost competitiveness and supply stability. The move is also interpreted as part of a longer-term strategy to diversify a supply chain currently concentrated on TSMC. Beginning with HBM4, “custom HBM”—in which the base-die design is tailored to the architecture and performance requirements of individual customers’ AI accelerators—is becoming increasingly important. For SK hynix, this creates a need to move away from an ecosystem concentrated around specific customers and foundries and broaden its ability to collaborate with a wider range of AI chip companies. There is also speculation that SK hynix’s cooperation with Intel could eventually expand beyond base-die manufacturing into advanced packaging. At Hot Chips, the high-performance semiconductor and computing architecture conference held in Silicon Valley, Lee Jae-sik, vice president of package engineering at SK hynix America, said the company is evaluating and comparing major advanced packaging technologies, including TSMC’s CoWoS-S and CoWoS-L as well as Intel’s EMIB. $INTC

Here are my thoughts from Advancing AI yesterday: Lisa opened by stating 35 quadrillion tokens are being consumed every month, up roughly 160x in two years. She mentioned that the curve is steepening, NOT FLATTENING. She mentioned that training is not dying. Compute being used to train frontier models is still growing 5x per year. However, 2026 is the first year inference is the larger consumer at around 60% of global compute (AI). Both can be true at once. What was interesting to me, and which I liked, were the TAM revisions. > AI accelerator market to be $1.4T by 2030, up from $AMD's own $500B from a year ago > Total high performance and adaptive compute TAM: approaching $2T by 2030 > Server CPU market: from ~$25B today to $220B by 2030 So it was confirmed, once more that you do not just run billions of agents on GPUs alone. CPUs run the loop. On hardware (Helios is in full production): > 72 instinct MI455X GPUs + 18 6th Gen EPYC Venice CPUs in one double-wide rack, tied together with Pensando networking > 31TB of pooled HBM4 per rack, 1.4PB/s aggregate memory BW > 2.9 exaflops FP4, 1.4 exaflops FP8 > 260TB/s scale-up, 43TB/s scale-out > vs. the competing next-gen rack: 10-15% more FP4 compute, 50% more HBM4 capacity and BW, 50% more scale-out BW Each MI455X is 320B transistors, 432GB of HBM4 at 19.6TB/s, TSMC's 2nm compute tiles over 3nm base dies. MI300 and MI350 have shipped as OAM modules on a universal baseboard. MI455X ships as an EAM, direct liquid cooled. That is the packaging level reason a 72 GPU rack-scale domain is possible. Shipments start at the end of Q3, ramping thru Q4 and into H1 2027. Also, the 18x lower $/tok is MI455X vs. MI355X, NOT against NVDA's. Against the leading competitive rack, the claim is up to 30% more tokens per dollar. OpenAI and Meta each at 6GW. Anthropic up to 2GW starting H1 2027, with up to a $5B investment into Anthropic. CBRS splitting prefill onto Helios and decode onto wafer-scale, which is oddly familiar to NVDA x Groq. Now, on software: > pushes AMD skills directly into Claude, Codex, Cursor, and Gemini so the agent understands AMD hardware natively. $AMD claimed 3.3x average inference and 2.4x training uplift > Hyperloom, an open-source agent that profiles and rewrites kernels E2E, lifted tok rate on the demo code by 38% > FlyDSL, a Python DSL for authoring GPU kernels that match hand-tuned HIP C++ So it looks to me, and sounded like, the CUDA moat is fading. AMD is using its own enterprise deployment as a case study: 43% cut to the tok cost and 2.9x faster responses. It was also neat to hear so much about local AI. Gorgon Halo goes to 192GB unified memory and runs 300B+ param models on an x86, shipping Q3. So, if you're in on $AMD I'd be watching 8/4 earnings and see if Helios units are recognized and EPYC commentary.

Morgan Stanley: We see the major customers of EMIB-M being Trainium3, upcoming Trainium 4 and its in-house server CPU. Average EMIB-T capacity is around 5kwpm in 2026, which we expect to further scale to 15-20kwpm in 2027 and 40-45kwpm in 2028. $INTC $AMZN