Samsung is reportedly developing next-gen HBM packaging for mobile on-device AI.
According to ETNews, Samsung is working on “Multi Stacked FOWLP,” combining advanced copper-pillar stacking with fan-out wafer-level packaging.
Today’s mobile LPDDR still uses copper wire bonding, which limits I/O to roughly 128–256 terminals and creates signal-loss, thermal, and power-efficiency bottlenecks.
Samsung’s VCS technology improves this by stacking DRAM dies in a staircase structure and connecting them with copper pillars. The new approach appears to push that further, aiming to bring HBM-like bandwidth closer to mobile devices.
$MU more than doubled its HBM market share in just one year, helping drive explosive growth across the memory industry as AI clusters scale globally.
Micron, SK hynix, and Samsung are all benefiting from surging HBM demand tied to almost $700B in AI infrastructure spending from $AMZN, $GOOGL, $META and $MSFT.
$MU $DRAM $TSM Holy Shit
2026: 12 HBM stacks per substrate
2029: 64 HBM stacks with SoW
That is a 5x structural expansion of HBM demand per system. The memory content per platform is not peaking. It is just getting started.
🚀 #Samsung# is reportedly working on next-gen mobile #HBM# packaging using ultra-high-aspect-ratio copper pillars and FOWLP, with bandwidth gains said to reach 15%–30%.💡More: 🔗
Advanced Logic, HBM and Advanced Packaging (CoWoS and CoPos) depends on Applied Materials.
TSMC depends on Applied Materials
Samsung depends on Applied Materials
SK Hynix depends on Applied Materials
Intel depends on Applied Materials
Terafab depends on Applied Materials
See you on the call tomorrow. $AMAT
Rumor: SK hynix has run into an issue with its HBM4, requiring a photomask revision for the 12nm base die. As a result, volume shipments could be delayed by more than one quarter, which would also impact shipments across the related supply chain.
$MU Mobile $DRAM contract prices are surging. Again.
LPDDR4X: +70-75% QoQ
LPDDR5X: +78-83% QoQ
HBM is eating Server DRAM wafers.
SOCAMM is eating Mobile DRAM wafers.
Nvidia got FAFOed multiple times with Rubin/Rubin Ultra design
- They pushed for higher pin speed HBM4, but Micron's & Hynix's base die were subpar, so they had to change plans & face delays (lower pin speeds)
- They pushed for a quad die Rubin Ultra design, yield and warpage issues forced them to switch to 2 die and 2+2 die MCM design
- They pushed for 16 Hi HBM4E for Ultra, yield issues forced them to come back down to 12 Hi
- They pushed for a dual profile 2.3kW/1.8kW Rubin, but indium-graphite TIM was unstable and now they are switching back to graphite TIM