📢 Packaging is emerging as a key growth driver for #AppliedMaterials#, with the company targeting >50% growth in 2026. Semiconductor equipment is also seen rising >30% YoY, supported by strength in memory tools led by DRAM wiring.💡More: 🔗

# 3D Packaging & **Onto Innovation (ONTO TP $397) Note * **Outlook:** 2026 revenue guided at **$1.3bn**; capacity supports **$2bn** by 2027. ### **3D Packaging Trend** We expect the shift to 3D for Nvidia Feynman, AWS Trainium, and Google V9 (Broadcom). * **Capacity Surge:** We forecast TSMC SoIC capacity to be 15KPM and 35KPM by end of 2026 and 2027. * **Tools:** **G5/3Di** tool shipments expected to jump from ~30 units in 2026 to >100 units in 2027. #ONTO#

Intel’s EMIB Packaging Is Growing Rapidly — Silicon Capacitors Are Taking Off Too Silicon capacitors are poised for explosive growth in the AI semiconductor space. Intel has been found to be planning a large-scale adoption of silicon capacitors starting next year, in order to enhance the performance of its in-house 2.5D packaging technology, “EMIB.” The most clearly visible source of demand is Google. Google plans to launch its next-generation AI accelerator, “v8e,” in the second half of next year, and has adopted an EMIB substrate with embedded silicon capacitors for that chip. With other Big Tech companies such as Amazon also currently applying EMIB, analysts say demand could increase sharply. According to industry sources on the 27th, Intel plans to apply silicon capacitors to its 2.5D packaging starting next year. Intel Adopts “Silicon Capacitors” for 2.5D Packaging… Google AI Chip Gets First Application 2.5D is an advanced packaging technology that inserts a thin-film interposer between the semiconductor and the substrate. Because it can connect circuits at higher density compared with conventional packaging that uses only a substrate, demand is rising in the AI and HPC fields. To improve cost efficiency in 2.5D packaging, Intel devised its own technology called EMIB. Rather than using a broad, spread-out interposer, EMIB connects chip to chip using a small silicon bridge. Since bridges only need to be placed where chip-to-chip connections are required, chips can be arranged more flexibly and efficiently. Recently, EMIB has been drawing attention as an alternative to TSMC, which had been leading the existing 2.5D packaging market. This is because TSMC’s 2.5D packaging capacity is suffering from a supply shortage amid the rapid development of the AI industry. Indeed, global Big Tech player Google is also paying attention to EMIB. Google has decided to adopt EMIB for its in-house AI semiconductor “v8e,” which it plans to launch in the second half of next year. Under this structure, TSMC handles chip mass production, MediaTek handles design and manufacturing support, and Intel handles packaging. However, there have been concerns that EMIB is gradually showing limitations in providing stable power supply for AI semiconductors, which consume large amounts of power. Accordingly, Intel plans to introduce new technologies such as silicon capacitors and through-silicon vias (TSV) to ensure stable packaging for the v8e. A capacitor is a component that stores and releases electricity in an electronic circuit. In the case of silicon capacitors, their resistance (ESL/ESR) is more than 100 times lower than that of conventional multilayer ceramic capacitors (MLCC), minimizing the signal loss that occurs in high-performance semiconductors. They can also be designed in an ultra-thin structure based on a silicon wafer, enabling high-density integration. A semiconductor industry official explained, “Because the voltage drop (the phenomenon of voltage decreasing) that occurs in the high-frequency region within AI chips is difficult to solve with MLCC, we understand that Intel is adopting silicon capacitors as a solution,” adding, “The relevant supply chain is now in place, and mass production is set to begin in earnest next year.” EMIB-T Is Already on a Growth Trajectory — The Related Ecosystem and Market Are Expanding Together Intel has also inserted TSVs, which serve as power-delivery channels, into the silicon bridge. The key point is that by using TSVs to shorten the power-delivery path between the substrate and the chip, Intel has improved power efficiency and signal integrity. Intel calls this “EMIB-T.” The industry expects the EMIB-T and silicon capacitor markets to grow rapidly. This is because Japan’s Ibiden — one of the major companies that mass-produces semiconductor substrates for EMIB-T — is aggressively pursuing capital investment. Previously, Ibiden had planned to build its Kawashima (Gama) plant in Gifu Prefecture as a substrate plant for Intel CPUs. However, it postponed that schedule and decided in the first half of this year to officially convert the Gama plant into a mass-production line for EMIB-T substrates. The investment is 220 billion yen (about KRW 2.1 trillion). In its recent earnings announcement, Ibiden stated, “Operation of the Gama plant will begin in 2027 and enter full-scale mass production in 2028,” adding, “EMIB-T substrate capacity is currently far short of demand. However, adding further capacity is quite difficult, so we are discussing options with our customers.” A semiconductor industry official explained, “Ibiden’s EMIB-T-dedicated line is being built with most of the investment coming from customers such as Google, Amazon, and Intel,” adding, “This demonstrates that AI semiconductors based on EMIB-T will grow significantly going forward, and silicon capacitors are likely to expand alongside them.”

TSMC Expands Outsourcing of Key Packaging Step CoW… Expected to Ease AI Chip Manufacturing Bottleneck TSMC is expanding outsourced production of a major process step for artificial intelligence (AI) chips. The move is seen as a step toward resolving the bottleneck in AI chip manufacturing. Much of the volume TSMC had been handling in-house is set to go to outsourced semiconductor assembly and test (OSAT) firms, and a large-scale wave of equipment investment is expected to follow. According to industry sources on the 4th, TSMC has decided to place additional CoW (chip-on-wafer) packaging volume — part of the CoWoS process used to manufacture AI chips — with ASE and other OSAT providers. In response, major OSAT companies are moving ahead with equipment orders to build new production lines. Purchase order (PO) discussions are also reportedly underway with Korean materials, components, and equipment suppliers. The specific investment scale has not been disclosed, but capacity is expected to be expanded substantially versus current levels. CoWoS is TSMC's 2.5D packaging technology, used in building AI chips. A processor (SoC) for AI workloads, such as a GPU, sits at the center with high-bandwidth memory (HBM) placed around it, and an intermediate substrate called an interposer is used to connect the two. TSMC refers to the step of attaching the chips to the interposer as CoW, and the step of bonding that interposer to the main substrate as WoS (wafer-on-substrate). Until now, TSMC has mainly outsourced WoS, the bonding to the main substrate. ASE, Amkor, and SPIL have been producing it under technology licenses from TSMC. Some CoW work was also outsourced, but only in limited volumes. The decision to significantly expand CoW outsourcing this time is attributed to the persistent bottleneck in AI chip manufacturing. Demand has surged as not only global AI chip designers (fabless firms) led by Nvidia, but also AI data center operators, move to develop and deploy their own custom silicon. TSMC is estimated to hold roughly 90% of the global AI chip manufacturing market. With demand continuing to grow and TSMC's own capacity insufficient to meet it, the company is looking to increase outsourcing. "TSMC has continued to invest in packaging capacity for AI chip manufacturing, but it is still being criticized for bottlenecks at the packaging stage," an industry official said. "This expansion of outsourcing is an attempt to scale up capacity together with its key OSAT partners, as market demand keeps expanding." As OSATs receiving CoW volume from TSMC ramp up equipment investment, back-end materials, components, and equipment suppliers are also expected to benefit. Investment is seen concentrating in particular on dicing — cutting wafers and interposers — and on the bonding processes that join wafers to interposers. According to multiple sources in the Korean equipment industry, discussions on supplying CoW-related tools are underway in the laser processing and bonding segments. $ASX $AMKR