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Neil Shah
@neil_shah
Co-Founder & Research VP @CounterPointTR | Technology Industry Analyst | Entrepreneur | @MITSloan | @UofMaryland @SmithSchool @ClarkSchool Alumni |
Joined April 2009
999 Following    8.5K Followers
Talking about packaging, have been digging into @intel XBM approach, fascinating me to understand different bottlenecks on how the engineers are trying to solve it. HBM ➡️ XBM Today, HBM relies on an ultra-wide parallel bus (1024–2048 bits), routing thousands of micro-wires demands an expensive Silicon Interposer (like TSMC CoWoS). The most expensive part (design)of HBM if you understand isn’t the DRAM chips it’s the massive piece of silicon sitting underneath them. It’s the hidden, cascading cost penalties, supply-constrained, thermal headaches that the interposer forces onto the entire system rather than just interposer $$ cost. Intel’s XBM (Cross-Batch Memory) looks to ‘omit’ the interposer entirely with two major architectural changes: 1️⃣ Serial UCIe over Wide Parallel Links instead of routing ~1,000 parallel wires, XBM converts data into high-speed serial UCIe streams @ 32 GT/s. (First diagram) Far fewer wires enables direct substrate routing. Thus no need for silicon interposer and stiffeners, shrinking Z-height & saving on packaging complexities and costs. 2️⃣ BEOL (Back-End of Line via TFTs ) DRAM (Moving the Memory Cells Up) from FEOL (Front-End of Line) - second diagram Standard DRAM builds its cells in the silicon base (FEOL), competing with logic for real estate. Intel shifts the 1T1C memory cells into the back-end metal layers (BEOL) using Thin-Film Transistors (TFTs). The base silicon is now 100% dedicated to logic and TSVs. 3️⃣ Serial chiplet links could end the traditional HBM interposers if this alternative of XBM from @Intel_Foundry takes off. However, there are a few of hurdles around XBM approach which needs to be addressed: 1️⃣ Latency Penalty & Fast SerDes causing issues around Thermals 2️⃣ Adding TFTs is not trivial inside BEOL and needs to be mastered 3️⃣ From Concept to Commercialisation: hearing it could take 2030 to reach that level to go mainstream and depends on an anchor client and memory partner adopting it with entrenchment of ecosystem around, JEDEC standards, CoWoS investments for HBM makes the switch difficult This is where Intel has been gaining good mindshare back to solving problems for the industry as a strong alternative to current incumbents. #Semiconductors# #HBM# #Intel# #Hardware# #UCIe# #Chiplets# #Packaging# $INTC $TSM $AMKR $ASX
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