🍽️ DRAM devouring Vera. ▪️1.5 TB LPDDR5X memory (1 Vera CPU) ▪️12 TB SOCAMM LPDDR5X memory (x8 Vera CPUS) Every time I see this Vera CPU tray, reconfirms the DRAM demand is here to stay as the role of CPU in the Agentic AI era grows day by day. 1️⃣ Rising Number of Agents, multiple Autonomous Loops Per Core: Demanding Orchestration and Concurrency 2️⃣ Thousands of Agents API Calls & Execution, State Management 3️⃣ Decision Making Graph Logic and Flow Control 4️⃣ Semantic Search (RAG) and Vector Processing $NVDA $ARM $INTC

Yes, as we have been tracking monthly, significant traction with domestic datacenter demand & rising per Gbit ASPs in Q2 2026 CXMT Bit growth in Q2 2026 : Total: +155% YoY Server: +383% YoY Lets see how Q3 pans out as CXMT key customers raise prices for their products which will boost Q3 further. #DRAM#

🚨The launch of the day!! @Xiaomi just unveiled the Xring O100 (玄戒O100) - first dedicated high-bandwidth AI accelerator for edge large models - Vertically stacks a 6nm NPU compute wafer with dual high-speed DRAM memory wafers (Wafer-on-Wafer 3D stacking). - Uses advanced Hybrid Bonding instead of conventional micro-bumps. •- Bonding pitch shrinks from ~50 μm all the way to 1.4 μm. - Creates 2.58 million high-speed physical pathways (TSV diameter just 0.7 μm). - Face-to-Face metal-layer direct connections open ultra-short “data wells” straight into the compute cores. - Paired with Xiaomi’s self-designed high-bandwidth matrix bus (HB-Matrix) and 14-core NPU, data flows between the NPUs and memory at extreme speed with dynamic topology switching (ring for prefill, broadcast for decode). - 1.22 TB/s near-memory bandwidth — 16× a flagship phone’s LPDDR5X - Up to 330 tokens/s edge inference (3B model in Xiaomi lab tests) - Designed for on-device LLMs for following Applications: - Smartphones - PCs - Robots - Xiaomi cars / intelligent driving systems - AI Cube prototype (paired with Xring O3 + D100), for models up to 120B parameters locally at up to 150W sustained 🗓️ The chip has completed silicon validation and is scheduled for commercial use in 2027. #Xiaomi# #XRing# #DRAM#

Talking about packaging, have been digging into @intel XBM approach, fascinating me to understand different bottlenecks on how the engineers are trying to solve it. HBM ➡️ XBM Today, HBM relies on an ultra-wide parallel bus (1024–2048 bits), routing thousands of micro-wires demands an expensive Silicon Interposer (like TSMC CoWoS). The most expensive part (design)of HBM if you understand isn’t the DRAM chips it’s the massive piece of silicon sitting underneath them. It’s the hidden, cascading cost penalties, supply-constrained, thermal headaches that the interposer forces onto the entire system rather than just interposer $$ cost. Intel’s XBM (Cross-Batch Memory) looks to ‘omit’ the interposer entirely with two major architectural changes: 1️⃣ Serial UCIe over Wide Parallel Links instead of routing ~1,000 parallel wires, XBM converts data into high-speed serial UCIe streams @ 32 GT/s. (First diagram) Far fewer wires enables direct substrate routing. Thus no need for silicon interposer and stiffeners, shrinking Z-height & saving on packaging complexities and costs. 2️⃣ BEOL (Back-End of Line via TFTs ) DRAM (Moving the Memory Cells Up) from FEOL (Front-End of Line) - second diagram Standard DRAM builds its cells in the silicon base (FEOL), competing with logic for real estate. Intel shifts the 1T1C memory cells into the back-end metal layers (BEOL) using Thin-Film Transistors (TFTs). The base silicon is now 100% dedicated to logic and TSVs. 3️⃣ Serial chiplet links could end the traditional HBM interposers if this alternative of XBM from @Intel_Foundry takes off. However, there are a few of hurdles around XBM approach which needs to be addressed: 1️⃣ Latency Penalty & Fast SerDes causing issues around Thermals 2️⃣ Adding TFTs is not trivial inside BEOL and needs to be mastered 3️⃣ From Concept to Commercialisation: hearing it could take 2030 to reach that level to go mainstream and depends on an anchor client and memory partner adopting it with entrenchment of ecosystem around, JEDEC standards, CoWoS investments for HBM makes the switch difficult This is where Intel has been gaining good mindshare back to solving problems for the industry as a strong alternative to current incumbents. #Semiconductors# #HBM# #Intel# #Hardware# #UCIe# #Chiplets# #Packaging# $INTC $TSM $AMKR $ASX