🔥 #CoWoS# expansion is accelerating beyond #TSMC#. #ASE’s# SPIL has broken ground on a nearly TWD 100B plant in Douliu to boost capacity, with first-phase operations set for 2028.💡More: 🔗

In an advanced-node production line (e.g. CoWoS, CoPoS), Applied Materials' cumulative equipment installed value can be at least comparable to ASML’s total installed value. Yet, $AMAT currently has 1/2 the market value of $ASML.

Advanced Logic, HBM and Advanced Packaging (CoWoS and CoPos) depends on Applied Materials. TSMC depends on Applied Materials Samsung depends on Applied Materials SK Hynix depends on Applied Materials Intel depends on Applied Materials Terafab depends on Applied Materials See you on the call tomorrow. $AMAT

Meta’s Muse is reigniting the CPU trade. $TSM’s CoWoS bottleneck is opening a window for Intel’s EMIB-T. Liwei and @regularwang break down the technology behind Intel’s all-in-one AI play, from CPUs and EMIB-T to 14A and optical I/O.

$INTC investors: $TSM’s Packaging Constraints Could Open Doors for $INTC’s EMIB-T TrendForce expects CoWoS-L to remain the mainstream AI chip packaging technology through 2028, citing its maturity and yield advantages. But larger interposers raise costs, and $TSM’s capacity constraints are pushing customers to consider $INTC’s alternatives. That gives EMIB-T a potential opening without requiring CoWoS-L to lose its lead. For chip designers adding more compute dies and HBM, packaging availability and cost could make a second supplier increasingly valuable. Sources

Rumor: Intel Malaysia took over some advanced packaging for TSMC due to a surge in orders for CoWoS packaging by a major mutual client, media report, adding ASE, Unimicron, Gudeng Precision and others are also expected to benefit from the move. TSMC is expected to ship more advanced chips as the packaging bottleneck eases. $INTC $TSM $ASX $GOOGL $NVDA #semiconductors#

- Global Unichip Corp. (GUC, has announced a 16 Gbps HBM4E PHY and Controller IP on TSMC N2P, targeting next-generation AI ASICs with support for CoWoS and 3D SoIC architectures. - Importantly, the 2nm designation refers to the ASIC-side HBM PHY and Controller IP implemented on TSMC N2P, not the DRAM process used to manufacture the HBM4E memory itself. - GUC says the HBM4E PHY and Controller design has been finalized and has already been adopted by a customer's AI ASIC, although the customer has not been disclosed. - The previous 12 Gbps HBM4 PHY and Controller on TSMC N3P is already silicon-proven, with GUC now extending the platform to 16 Gbps HBM4E. - GUC CTO Igor Elkanovich says its HBM4E solution delivers 3.3x bandwidth, 2.6x area efficiency, and 1.4x power efficiency versus HBM3E, based on GUC's IP comparison. - The platform goes beyond conventional CoWoS HBM connectivity by supporting a face-up HBM PHY for TSMC SoIC-X, including TSVs for I/O, power, ground, and feedthrough power delivery to logic dies stacked above the PHY. - GUC is positioning HBM4E together with face-up UCIe and GLink-3D as a broader 3D ASIC interface platform, enabling integration across HBM, chiplets, and vertically stacked logic. - The timing is notable because SK hynix announced in June 2026 that it had shipped 12-layer HBM4E samples operating at up to 16 Gbps per pin to major customers, meaning both the memory and ASIC/IP ecosystems are now preparing for the same performance generation.

As AI chip sizes grow and integrate more HBM, 2.5D packages are getting larger, straining TSMC’s CoWoS capacity. Could Intel’s lower-cost EMIB-T shift CSP orders? 💡More analysis from #TrendForce#: 🔗