In an advanced-node production line (e.g. CoWoS, CoPoS), Applied Materials' cumulative equipment installed value can be at least comparable to ASML’s total installed value. Yet, $AMAT currently has 1/2 the market value of $ASML.

Advanced Logic, HBM and Advanced Packaging (CoWoS and CoPos) depends on Applied Materials. TSMC depends on Applied Materials Samsung depends on Applied Materials SK Hynix depends on Applied Materials Intel depends on Applied Materials Terafab depends on Applied Materials See you on the call tomorrow. $AMAT

On the potential of an NVIDIA HBM downspec (option) Our model suggests that a broad HBM downspec across NVIDIA’s Rubin portfolio could support roughly 30% to 50% more GPU shipments from the same available pool of HBM bits, assuming CoWoS and compute-die supply keep pace. If those GPUs are deployed, power becomes the next question. A 30% to 50% uplift on roughly 7 million Rubin units across 2027–2028 would add 2.1–3.5 million GPUs. At 2kW per accelerator, that implies roughly 4–7GW of incremental ex-China chip-level power demand across the two years, or about 2–3.5GW annually if deployment is evenly split. Current assumption right now in accelerator forecast, is we need to energize (global ex-China) 26 GW in 2027 and 32-35GW in 2028.

$TSM $MU $SKHY $DRAM TSMC's SoW-X: 64 HBM stacks on a single wafer. Today's best? 12. Today (CoWoS): 8 to 12 HBM stacks 2028 (CoWoS): 20 HBM stacks 2029 (CoWoS): 24 HBM stacks 2029 (SoW-X): 64 HBM stacks The leap is staggering.

$TSM $ASX $INTC "TSMC is facing a surge in AI chip orders using its advanced packaging technology, such as CoWoS, but competitors such as Intel are benefiting as the Taiwanese semiconductor powerhouse is unable to keep up with demand." "Leading this advanced packaging race is none other than TSMC, whose CoWoS (Chip-on-Wafer-on-Substrate) had a head start over the competition and has been the go-to choice for several years. As demand shoots through the roof, even the Taiwanese giant is facing the brunt of existing bottlenecks within the supply chain and is unable to meet demand." "Intel is aiming to become the 2nd largest advanced packaging provider with its EMIB technologies that are poised to offer several benefits over CoWoS. Furthermore, a wave of Taiwanese packaging and test companies, namely ASE, SPIL, Powertech, and KYEC, is also taking advantage of the situation as TSMC orders face a spill-over effect." "Reports indicate that Intel, with active support from the US government, is aggressively pursuing advanced packaging, and Taiwanese packaging and testing companies, including ASE, SPIL, Powertech, and KYEC, are also taking advantage of the spillover effect of orders." "We have already seen reports that NVIDIA will move advanced packaging orders to Intel for its next-gen Feynman GPUs. These are anticipated to utilize Chipzilla's improved EMIB technology."

What's the next step change in chip packaging technology? @bubbleboi: "The main difference between EMIB and CoWoS is CoWoS relies on what we call silicon interposers. They're like these huge plates where you put the chips on, and you start etching channels in between through the interposers." "An effect of that is that heat dumps into the interposers, just like anyone knows when they heat up popcorn, things expand and contract, and this creates worse yield." "NVIDIA's already seen this. Part of the reason why Blackwell had trouble ramping was all thermals, the package warping. That's a huge issue." "I think even TSMC knows it's a huge issue because in their further along roadmap, they don't really plan on adopting that for much longer. They're now going to a more Intel style thing where you use little bridges... smaller pieces of silicon to connect just the relevant parts." "What that effectively does is cut your costs 'cause you're using way less silicon, the thermals, the communication, it's centralized in one area."

I didn’t realize this, but it looks like AWS may be using EMIB for a lower-end version of Trainium through MediaTek. Similar to the TPU v9 program handled by MediaTek, next-generation Trainium seems likely to use both EMIB and CoWoS. $INTC

TSMC Expands Outsourcing of Key Packaging Step CoW… Expected to Ease AI Chip Manufacturing Bottleneck TSMC is expanding outsourced production of a major process step for artificial intelligence (AI) chips. The move is seen as a step toward resolving the bottleneck in AI chip manufacturing. Much of the volume TSMC had been handling in-house is set to go to outsourced semiconductor assembly and test (OSAT) firms, and a large-scale wave of equipment investment is expected to follow. According to industry sources on the 4th, TSMC has decided to place additional CoW (chip-on-wafer) packaging volume — part of the CoWoS process used to manufacture AI chips — with ASE and other OSAT providers. In response, major OSAT companies are moving ahead with equipment orders to build new production lines. Purchase order (PO) discussions are also reportedly underway with Korean materials, components, and equipment suppliers. The specific investment scale has not been disclosed, but capacity is expected to be expanded substantially versus current levels. CoWoS is TSMC's 2.5D packaging technology, used in building AI chips. A processor (SoC) for AI workloads, such as a GPU, sits at the center with high-bandwidth memory (HBM) placed around it, and an intermediate substrate called an interposer is used to connect the two. TSMC refers to the step of attaching the chips to the interposer as CoW, and the step of bonding that interposer to the main substrate as WoS (wafer-on-substrate). Until now, TSMC has mainly outsourced WoS, the bonding to the main substrate. ASE, Amkor, and SPIL have been producing it under technology licenses from TSMC. Some CoW work was also outsourced, but only in limited volumes. The decision to significantly expand CoW outsourcing this time is attributed to the persistent bottleneck in AI chip manufacturing. Demand has surged as not only global AI chip designers (fabless firms) led by Nvidia, but also AI data center operators, move to develop and deploy their own custom silicon. TSMC is estimated to hold roughly 90% of the global AI chip manufacturing market. With demand continuing to grow and TSMC's own capacity insufficient to meet it, the company is looking to increase outsourcing. "TSMC has continued to invest in packaging capacity for AI chip manufacturing, but it is still being criticized for bottlenecks at the packaging stage," an industry official said. "This expansion of outsourcing is an attempt to scale up capacity together with its key OSAT partners, as market demand keeps expanding." As OSATs receiving CoW volume from TSMC ramp up equipment investment, back-end materials, components, and equipment suppliers are also expected to benefit. Investment is seen concentrating in particular on dicing — cutting wafers and interposers — and on the bonding processes that join wafers to interposers. According to multiple sources in the Korean equipment industry, discussions on supplying CoW-related tools are underway in the laser processing and bonding segments. $ASX $AMKR

Korea, Eugene Investment & Securities: On the NVIDIA Rubin Ultra HBM despec NVIDIA appears to be discussing a plan to configure the main version of Rubin Ultra with a 2 die structure, HBM4 8Hi, and 8 stacks, and to add an HBM4E 8Hi version at a later point. Assuming NVIDIA's 2027 CoWoS capacity allocation is 1,200k, NVIDIA's accelerator output is estimated at 9.9M units and Rubin Ultra output at 1.6M units. If Rubin Ultra shifts from HBM4E 12Hi 384GB to HBM4 8Hi 192GB, NVIDIA's 2027 HBM demand would be revised down by roughly 10%, from 24.1bn Gb to 21.6bn Gb, and total HBM demand could decline by about 4%. Of course, this assumption does not reflect the possibility of a further expansion in accelerator output. That said, we judge this despec to be a strategy for producing more accelerators out of a limited pool of HBM bits, as the increase in HBM supply from DRAM makers has failed to keep pace with the speed of TSMC's front end and back end capacity expansion. DRAM makers find it difficult to expand HBM capacity flexibly because of the extreme shortage in commodity DRAM. With consumer set makers in smartphones and PCs experiencing production disruptions due to memory shortages, it is also not easy for memory makers to cut allocations to these customers any further.

If $AMD wins, $TSM Advanced Foundry Process and Advanced Packaging win. Also a win for $DRAM as it packs 50% more memory than competitors. “AMD unveils its sixth-generation EPYC 9006 server CPU and Instinct MI455X GPU, expanding its AI portfolio across agentic AI, cloud computing, enterprise, and high-performance computing (HPC). … the move is expected to drive demand for TSMC’s advanced packaging technologies, including CoWoS-L and SoIC.” “AMD notes that the EPYC Venice processor has entered volume production on TSMC’s advanced 2nm process technology, while the MI455X is built using TSMC 2nm and 3nm FinFET technologies.” “The MI455X integrates 320 billion transistors using multiple advanced packaging technologies. Four Accelerator Complex Dies (XCDs) are hybrid-bonded onto each Fabric and Cache Die (FCD), while the two FCDs are interconnected with 12 HBM4 stacks, two I/O dies, and each other using TSMC’s CoWoS-L packaging technology.” “Some high-end EPYC Venice models are reportedly expected to adopt TSMC’s CoWoS-L packaging and be manufactured at TSMC’s Kaohsiung Fab 22, with production expected to ramp in the second half of 2026 to support growing demand for agentic AI servers.” “CoWoS-L capacity remains tight. … some Chip-on-Wafer (CoW) orders are expected to be outsourced to ASE, while TSMC and OSAT providers continue expanding CoWoS capacity with visibility extending through 2027 and 2028.” “AMD’s MI450, MI455X, and future AI chips are expected to boost SoIC (System-on-Integrated-Chips) demand. Institutional investors … estimate that TSMC’s SoIC capacity will reach 15,000–20,000 wafers per month by the end of 2026, before doubling again by the end of 2027.” “AMD’s Instinct MI455X adopts HBM4 memory, increasing capacity by 50% from 288GB of HBM3E on the MI350 series to 432GB. Memory bandwidth also rises to 22.3 TB/s, up 2.8× from 8 TB/s on its predecessor.” “The MI455X delivers up to 40 PFLOPs of FP4 and 20 PFLOPs of FP8 performance—roughly doubling the compute capability of the MI350 series. By comparison, Nvidia’s Rubin GPU provides 50 PFLOPs of FP4 and 17.5 PFLOPs of FP8 performance.” (Nvidia Rubin is noted with 288GB HBM4 and up to 22 TB/s bandwidth.)