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A great week in Taipei at SEMICON Taiwan 2026. At the Memory Executive Summit, d-Matrix Vice President Chris Nicol joined leaders from across the semiconductor ecosystem to explore how memory is becoming an increasingly important part of AI system architecture. Thank you to everyone who connected with us in Taipei for the thoughtful conversations. #SEMICONTaiwan# #AIInference# #AIInfrastructure#
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👀 #SEMICON# Taiwan kicks off this week, bringing together #Google#, #Microsoft#, #NVIDIA#, #AMD#, and #MediaTek# as #CPO# and silicon photonics take center stage. What other key areas should be on your radar? 💡More: 🔗
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$MU $SKHY $DRAM Samsung’s SEMICON Taiwan 2026 memory roadmap. Take it with a grain of salt. These are all in R&D stage. Feasibility and specs are not guaranteed. HBM5 “the company’s HBM5 is targeting 2× the performance and 20% higher performance per watt versus HBM4E” “The performance gains will be paired with a 20% reduction in thermal resistance” Base die moving from 4nm (HBM4/HBM4E) to Samsung’s in-house 2nm node Preparing 12-, 16- and 20-layer DRAM stacks; mass production expected around 2028 zHBM “targeting 8× the performance and 3× the performance per watt of HBM4E” Aims to “reduce thermal resistance by 75%–90%” “stacks memory directly on top of the processor instead of placing memory beside the AI accelerator (xPU)” “By shortening the distance data must travel, the architecture delivers higher bandwidth and improved power efficiency” Expected launch after 2029 zNAND-O Targeted for sampling in 2028 “aims to deliver 10× the bit density of DRAM for large-scale data storage, while offering 7× the read bandwidth and power efficiency of NAND” “designed to meet the growing AI demand for DRAM-like speed and NAND-like capacity” CUBE strategy (Jangseok Choi) Four priorities: Capacity, Utilization, Bandwidth and Efficiency Capacity: expand memory vertically without enlarging PCB footprint Utilization: “3D memory as more than simply stacking layers,” optimize architecture and logic/memory placement to cut latency Bandwidth: “shorten die-to-die distances by replacing horizontal data paths with vertical high-speed channels” Efficiency: “minimizing the energy required to move each bit of data and maximizing performance per watt”
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Some key notes coming out of SEMICON Taiwan: > Sales of optical transceivers are projected to grow by 25% in 2025 compared to 2024, and are expected to grow by another 50% in 2026. Among them, the market for high-end 100G and above speeds doubled in 2024 and is expected to grow by another 60% in 2025. > Silicon photonics has become the mainstream technology, and its market share is expected to exceed 50% by 2027. > A manufacturer announced that it will begin mass production of CPO in the second half of this year. > Real bottleneck for large-scale deployment lies in other parts of the supply chain, including lasers, optical fibers, fiber optic connectors, and product testing. $TSEM $LITE $COHR $MTSI $AAOI
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Is anyone else going to SEMICON Taiwan? I’m on my way to the airport now to catch my flight to Taiwan.
Hanmi Semiconductor is showing a big AI packaging lineup at SEMICON Taiwan. The company is already No.1 in HBM TC bonders and now pushing deeper into 2.5D equipment for AI chips, plus HBM4 tools and a next-gen Wide TC bonder for larger DRAM dies. Hanmi Semiconductor is showcasing five models of 2.5D packaging equipment: FC Bonder 3.5 FC Bonder 75 2.5D TC Bonder 40 C2S 2.5D TC Bonder 40 C2W 2.5D TC Bonder 120 Among these, the FC Bonder 3.5, FC Bonder 75, and 2.5D TC Bonder 40 C2S and C2W have been released sequentially since the end of last year and are being supplied to global foundry and OSAT companies for mass production, while the 2.5D TC Bonder 120 is scheduled for release soon. Hanmi Semiconductor official stated, "Semicon Taiwan is a global event where AI semiconductor technologies converge," adding, "Hanmi Semiconductor will lead the growth of the AI ​​semiconductor market by expanding the supply of advanced packaging equipment not only for its globally leading HBM TC Bonder but also for the AI ​​system semiconductor market." #HanmiSemiconductor# #HBM# #AI# #Semiconductors#
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Shanghai Cooperation Organization summit, Semicon Taiwan, Shein listing
$TSM $MU $SKHY $NVDA TSMC Senior VP and Co-COO Hou Yongqing (Cliff Hou) at SEMICON Taiwan 2026 On the speed of AI demand Compared with the past 30 years, he has “never seen demand grow at such a rapid pace and at such high frequency.” If equipment demand at the end of last year was 1x, it rose to 1.5x after one quarter and reached 1.9x by July—a 90% increase in just over half a year, nearly doubling. On the ecosystem challenge “How the entire Taiwan semiconductor ecosystem can cope with such rapid demand growth in just six months is a major challenge we currently face.” On technology and collaboration AI’s need for computing power and energy efficiency is driving packaging and system-level performance “much faster than before.” The supply-chain model must change: “We must ensure that the performance achieved at one stage can still be realized at the next partner’s stage.” This requires “a brand-new model of cooperation.” On fab expansion TSMC is simultaneously building 13 fabs in Taiwan—“something we have never done before”—plus another 5–6 overseas, for a total of nearly 20. Previously the company typically built only 4–5 at a time. “Even so, it is still not enough to meet demand.”
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Agentic AI is changing what the data center needs from the CPU. At SEMICON Taiwan, CK Tseng shared how Arm is helping the ecosystem scale AI infrastructure through more efficient CPUs, custom silicon, chiplets and tighter system integration.
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$MU $SKHY AI is Memory Bound. Period. At SEMICON Taiwan 2026, $GOOGL Cloud's Nikhil Cherian said high performance memory now makes up over 75% of an AI server's hardware bill of materials. AI is shifting from compute bound to MEMORY BOUND as multimodal and MoE architectures scale. Google's response is a dual track approach. The inference focused TPU 8i packs 288GB of HBM with 384MiB of on chip SRAM to keep KV cache local. The training focused TPU 8t links 9,600 chips into a shared HBM pool of up to 2PB. $DRAM and NAND combined are projected to hit 47% of CSP capex in 2026, rising to 68% in 2027. Server DRAM contract prices are expected to surge roughly 270% this year.
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