Sony's chip unit (Imaging & Sensing) posted a record high operating profit of ¥154.6 billion (US$980M) in the 2nd quarter, up 12% year-on-year despite sales falling 6% to ¥577.6 billion (US$3.66B), media report, adding Sony's CFO said smartphone demand fell about 20% vs last year, partly because of memory prices. Sony raised the unit's full-year profit forecast to ¥450 billion, up by ¥30 billion. $SONY $TSM #semiconductors#

Democrats might be able to ban American superintelligence, but they can't ban China's. Do you really think an ASI trained on walled-off data will have your best interests at heart? Think again. The next generation of Americans better get ready to learn Chinese.

TrendForce forecasts demand for more than 62 million CPO and NPO optical engines in 2028, with wafer qualification, faster assembly and shorter testing times in 2027 determining whether suppliers can support that ramp. About 80% of the projected demand comes from scale-up interconnects linking accelerators within a compute cluster. The wafer numbers show why qualification matters. TrendForce puts nominal photonic integrated circuit (PIC) wafer capacity at roughly 430,000 wafers in 2027, with effective supply of about 80,000 after accounting for customer qualification and platform validation. It forecasts demand of around 150,000 wafers in 2028. Packaging and testing need productivity gains too. The active alignment throughput of just six units an hour and calls for a shift toward passive alignment. Optical-component testing needs to fall from roughly 100 seconds per unit to under 30 seconds, alongside parallel testing. We’re watching qualified wafer supply and assembly throughput alongside optical-engine shipment forecasts. Adding nominal capacity will only support the projected ramp as platforms pass qualification and packaging and testing lines increase output.

FT scoop: China blocks SoftBank’s $5.4b takeover of ABB’s robotics division * NDRC informed Softbank the decision in a recent change of heart * China is ABB's biggest market for robotics, mostly made in China. Co employs ~12,700 in the country

Key reading on days like this. The main idea from Pástor and Veronesi is that prices fall when a technology gets big enough that its risk becomes risk for the whole market. That can happen even when the demand data is fine.

Everyone talks about co-packaged optics as the future of AI networking, but most explanations only cover one piece of the system. What's missing is a holistic understanding of how all the pieces fit together. CPO isn't just a purely photonic problem, but a complex system-level co-design challenge involving optics, mixed signal circuits, fabrication, and packaging. I wrote an all-in-one technical overview that connects these disciplines and explains the major engineering challenges involved. This article covers: - Advanced packaging and FAU challenges - Semiconductor fabrication and manufacturing - Light manipulation and photonic devices - Light generation and popular laser architectures - EIC architectures for the driver and trans-impedance amplifier.

Saizeriya might be the only company in the world to be praised and even thanked by customers for raising prices when they finally announced it yesterday. It truly reflects how special Saizeriya is. I just published Part 2 of my Saizeriya deep dive, breaking down their own version of ‘scale economies shared’, a flywheel built over 50 years, predating Amazon or Costco! I apologise for the length but I hope you can see it as a result of the multitude upon which their moat is built upon. One that betrays economic theory we’re often taught. They are the Anti-Private Equity. And all the small decisions they’ve made over time have created a cost structure that will be almost impossible to replicate, let alone deliver the quality they do. Find it in the usual place. 🍝🍝🍝🍕🍅

問了一下AI 法棍(baguette)的物理參數，再看了research paper驗證了數據 標準法棍長約60cm 剛性(Young’s modulus): 新鮮法棍10–50 kPa，放久後達到70-100 kPa。木棍達超過10MPa yield stress: 幾 kPa 結論： 用法棍打人沒有任何痛感，被攻擊者只會感受到被輕拍了一下，而且一打法棍就會deform，是一種愛心打人工具。適合和平示威者hit-and-run時使用

For best thermal performance of AI Accelerators, the cold plate should be co-designed with the physical design of the silicon and the package. On-chip physical designers should be cognizant of potential hotspots and place power-hungry blocks in such a way to minimize hotspots and uniformly distribute heat throughout the package. Source: Y. Hang "Pushing the Single-Phase Cold Plate Limit" -