Theres a difference between sophistication and the asthetic of sophistication. Most people attend cultured events and seminars not out of genuine curiosity, but for signaling purposes to look cultured. There are a few dead giveaways people do this, such as asking at the beginning of an event, "what other events do you go to" and if they immediately lead with where else they've been. But not everyone does this, and those are often the quiet ones off to the side, often fed up with performative sophistication. Just tonight, I was just describing my website to a non tech person who was genuinely curious about how tokens flow through AI infrastructure. I kept the conversation at a very high level since he didn't have a technical background and was still able to share trends like optical for improving AI compute due to copper limits. I totally understand most people won't have a PhD background in most topics. However, I think grappling with discomfort goes a long a way to making yourself increasingly receptive to understanding more complex topics and cultivating your taste.

China’s AI-safety trajectory is not necessarily a delayed version of America’s. [1/6] People seem to have this mental model: Chinese models trail US models in capability by a given number of months and are involved in similar safety incidents after a delay. Whether this is true matters for what Chinese AI safety communities can contribute.

- Lightmatter officially introduced Passage L20 CPX on September 17 and joined the Open CPX MSA, describing the product as the first bidirectional Open CPX optical engine for AI infrastructure. - Passage L20 CPX uses 1311 nm and 1331 nm wavelengths to carry transmit and receive traffic over the same single-mode fiber, cutting fiber and connector requirements by roughly 50% versus conventional UniDi architectures. - The module is designed for 6.4 Tbps Tx plus 6.4 Tbps Rx, or 12.8 Tbps aggregate bandwidth, using 32 optical lanes per direction at a 212.5 Gbps PAM4 line rate with more than 500 meters of SMF reach. - In Lightmatter's 512-GPU scale-up pod model, the architecture reduces fiber count from roughly 131,072 to 65,536 while eliminating approximately 16,000 connectors and more than 200 miles of fiber. - Lightmatter estimates that BiDi could reduce total scale-up interconnect network spending by roughly 15%, although this figure comes from internal modeling and will vary by topology and deployment configuration. - Importantly, this is not yet a volume-production product. Passage L20 CPX evaluation kits are expected to ship to customers in Q1 2027, and the disclosed specifications remain preliminary. - The announcement follows Lightmatter's June entry into NVIDIA's NVLink Fusion ecosystem and its August launch of an OCP CPO architecture effort targeting AI systems scaling from 72 to more than 1,024 nodes.

Especially appreciate all the Sunbaes' shoutouts along the way! @pequityresearch @damnang2 @ren_stocks @SaiseiInvesting @JoeyOnMarkets @photonjaeger @RYANHINGSHING @ShanghaoJin @cherryPayment @Leoskie_L the whole point of running my X account is to stay connected with you all! Arigatou ! 🙏

@davinbirdi @jwt0625 Stealth dicing leaves a lot of particles when the wafer is snapped. Also the waveguides are on the top of the wafer, which won’t have a perfect edge. The best technique would avoid polishing and allow for wafer scale testing.

The most important argument here is not simply that the OCS market is growing, but that market growth does not automatically translate into durable revenue or market share for today’s suppliers. $LITE currently benefits from manufacturing and customer-qualification experience, while $COHR, POLATIS and integrated OCS approaches are creating new competitive paths that could change where value accrues. Another important distinction is that moving from 800G to 1.6T and beyond does not necessarily require replacing the OCS. That makes port count, deployment volume, merchant share and manufacturing economics more useful variables for evaluating the OCS opportunity than bandwidth growth alone.

- IPronics validates silicon photonics switch performance with datacenter-scale 1.6T signal throughput - Demonstrates technology readiness for high-speed optical interconnect applications in data centers > IPronics is advancing silicon photonics technology through practical validation at relevant datacenter signal levels, which indicates progress toward commercial optical interconnect solutions. > This test result supports the company's competitive position in the growing optical switching market for data centers.

Latitude divides the optical-interconnect design space into five scales: waveguides with roughly 0.5 µm core cross-sections; device libraries with footprints of around 10–500 µm; optical engines in the 10–25 mm range; packages in the 50–80 mm range; and finally the rack, at roughly two meters. Its central idea is straightforward: from waveguide to rack, each physical scale sets constraints for the next one; from rack back to waveguide, measured device behavior must continuously be used to recalibrate the models.

AI doomers bring the volatility. Liwei brings the CPO testing watchlist. Let the panic give you a better entry. Do the homework, pick your names, and have the conviction to act. Follow Liwei and @RegularWang. Let’s see who’s smiling next month.

Thanks @photonjaeger for sharing such great insights! Connecting the dots between TSMC's supply chain and today's news from Unimicron, Ramping-up in high-end ABF substrates signals the start of the semiconductor industry's typical 6- to 9-month advance procurement and inventory prep cycle. IYKYK $LITE $MRVL $COHR $AAOI

Back in March, I wrote about a less-discussed beneficiary of NVIDIA's shift toward silicon photonics: testing. Six months later, that thesis is moving from roadmap to production. $NVDA's Spectrum-X Ethernet Photonics for Vera Rubin is now in production, while the surrounding CPO test ecosystem is rapidly filling out: $LITE / $COHR → lasers & optical components $FORM → optical/electrical wafer probing & KGD $AEHR → wafer-level burn-in & reliability screening $TER → wafer-to-optical-engine-to-CPO automated test $KEYS → photonic characterization & validation Advantest / $VIAV / SENKO → CPO module & final test The important change is that the bottleneck is no longer just building the photonics. It is testing every photonic component before increasingly expensive heterogeneous integration, and then testing the completed CPO module at production throughput. That is exactly why the test content per optical link should continue rising as CPO moves into HVM.